公开(公告)号：FR2802668B1

公开(公告)日：2002-02-08

申请号：FR9915795

申请日：1999-12-15

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK

IPC: G06F1/00 ,  G06F7/58 ,  G06F12/14 ,  G06F13/38 ,  G06F21/55 ,  G06F21/62 ,  H04L9/10

Abstract: The secure data transfer operates in a programmable circuit containing a controller (UC), ROM and RAM, connected by a data bus (DBUS). N octets of secret data are transferred over the data bus, and the octets are sent in a different order each time the data transfer is made, using a transfer rule that has a parameter chosen at random before each transfer, using a random number generator (GA).

公开(公告)号：FR2802669A1

公开(公告)日：2001-06-22

申请号：FR9915796

申请日：1999-12-15

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK

IPC: G06F12/14 ,  G06F1/00 ,  G06F13/38 ,  G06F21/55 ,  G06F21/62 ,  H04L9/34

Abstract: The secured data transfer operates within a programmable circuit containing a processor, controller (UC), ROM and RAM, with a data bus (DBUS) connecting the memories. N octets of secret data are transferred over the data bus, and the octets are sent in a different order each time the data transfer is made, under control of a random number generator (GA).

公开(公告)号：DE602006011083D1

公开(公告)日：2010-01-28

申请号：DE602006011083

申请日：2006-07-05

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE-YVAN ,  POMET ALAIN

IPC: G06F11/00 ,  G06F21/75 ,  G06F21/77 ,  G07F7/10

Abstract: The method involves triggering a temporary counter (TIMER), which counts a data account based on instructions following a main program (Pg), during an execution of instruction of the main program. An instruction of a secondary program, depending on the result of the main program, is executed if the counter reaches its account, where the result of the main program is an arithmetic result. An independent claim is also included for an integrated circuit for implementing a protection execution method.

公开(公告)号：DE60324351D1

公开(公告)日：2008-12-11

申请号：DE60324351

申请日：2003-04-23

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK

IPC: G06F1/00 ,  G06F21/52

Abstract: The control of program execution associates with each operator an initial and a final numeric code, linked by a degradation function (DEG). The degradation function is applied to contents of a register (R) initialized at the start of each instruction with the initial code. After execution of each instruction, coherence between contents of the register and final code of the operator is tested.

公开(公告)号：DE602005003258T2

公开(公告)日：2008-09-18

申请号：DE602005003258

申请日：2005-04-22

Applicant: ST MICROELECTRONICS SA

Inventor： LLARDET PIERRE-YVAN ,  TEGLIA YANNICK

IPC: G06F21/72 ,  G06F21/75 ,  G06F21/77

Abstract: The process involves starting an execution of a calculation, and starting another execution of the same calculation once the former execution has freed a block and its process in a second. The executions are synchronized such that the latter execution uses a hardware block only when the former execution passes to the next block. The identity between the two results is verified at the end of execution of both the calculations. An independent claim is also included for a chip card.

公开(公告)号：DE60314055T2

公开(公告)日：2008-01-24

申请号：DE60314055

申请日：2003-07-02

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  ROMAIN FABRICE ,  TEGLIA YANNICK ,  SIRTORI LAURENCE

IPC: H04L9/06

公开(公告)号：DE60034921T2

公开(公告)日：2008-01-17

申请号：DE60034921

申请日：2000-12-06

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK

IPC: G06F12/14 ,  G06F1/00 ,  G06F7/58 ,  G06F13/38 ,  G06F21/55 ,  G06F21/62 ,  H04L9/10

Abstract: The secure data transfer operates in a programmable circuit containing a controller (UC), ROM and RAM, connected by a data bus (DBUS). N octets of secret data are transferred over the data bus, and the octets are sent in a different order each time the data transfer is made, using a transfer rule that has a parameter chosen at random before each transfer, using a random number generator (GA).

公开(公告)号：DE602004000562D1

公开(公告)日：2006-05-18

申请号：DE602004000562

申请日：2004-07-09

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE-YVAN

IPC: G06F11/00 ,  G06F1/00 ,  G06F11/07 ,  G06F21/52 ,  G06F21/71

Abstract: A non-volatile memory (22) stores value of the verification of an invariant, and periodically recalculates the value in volatile memory. A circuit (21) holds an invariant in normal operation of the processor (1), and compares with stored invariant to detect loss of invariant and occurrence of disturbance in processor. An independent claim is also included for integrated processor.

公开(公告)号：DE60207818D1

公开(公告)日：2006-01-12

申请号：DE60207818

申请日：2002-02-06

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE ,  TEGLIA YANNICK

IPC: G09C1/00 ,  H04L9/06

Abstract: A secured method of cryptographic computation to generate output data from input data and from a secret key includes a derived key scheduling step to provide a derived key from the secret key according to a known key scheduling operation. The method also includes a masking step, performed before the derived key scheduling step, to mask the secret key so that the derived scheduled key is different at each implementation of the method. The present method and component can be used in transfer type applications, such as bank type applications.

公开(公告)号：FR2872357A1

公开(公告)日：2005-12-30

申请号：FR0451325

申请日：2004-06-24

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE YVAN ,  TEGLIA YANNICK

IPC: H03K3/84

Abstract: L'invention concerne un procédé et un circuit de détection d'une éventuelle perte de caractère équiprobable d'un premier flux de bits de sortie (NBS1) issu d'au moins un premier élément de normalisation (3) d'un flux de bits initial (BS), consistant à soumettre le flux initial à au moins un deuxième élément de normalisation (4) de nature différente du premier, apparier (8), bit à bit, les flux issus des deux éléments, et vérifier (5, 9) l'équirépartition des paires d'états différents.