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公开(公告)号：FR2799044B1
公开(公告)日：2001-12-14
申请号：FR9912148
申请日：1999-09-29
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , BERTRAND BERTRAND , NAURA DAVID
Abstract: The method for selecting an access line of a memory of EEPROM type with serial access, implemented in the form of an integrated circuit, includes a selection from the group of access lines (AL0-AL7) of the same nature, e.g. the bit lines or the word lines, by a line code for p (=3) bits associated with each access line of the group, and comprises the following steps: (a) the activation of all access lines of the group; (b) the reception, by the intermediary of an input of serial data (D1), of a bit (Ai) of determined rank of code of access line to select; and (c) the de-activation of a part of other access lines as a function of bit (Ai). The latter two steps, (b) and (c), are repeated successively p times for each bit of line code, so that at the end of p iterations only the selected access line remains activated. The access lines which are de-activated at step (c) are the access lines which line code presents a bit rank i of value different from that of the received bit at step (b). The group of access lines comprises 2p lines, and half of lines still activated is de-activated at each iteration. All access lines are simultaneously activated, at step (1). The bits of line code received at step (b) are included in the address bits of memory word on which an operation defined by an instruction received according to a serial protocol is carried out. The set of access lines is an ordered set, according to increasing or decreasing binary values of associated line codes. A decoder of access lines implementing the method comprises latches (10-107), each coupled to an access line (AL0-AL7), each latch comprising switching, activation and de-activation means operated as a function of selection signals (Bit0,Bit1,Bit2,Bit0 bar, Bit1 bar, Bit2 bar), the means for putting all latches into active state, and the means for the generation of selection signals as a function of bits of line code. The switching means of a latch comprise an inverter connected between input and output, thee activation means comprise a controlled interrupter, and the de-activation means comprise the decoding means including p MOS transistors with the gates connected to the selection inputs, and one with the gate connected to the output of latch. The means for the generation of selection signals comprise 2p logic gates of NAND type (NE1-NE6), the first p gates receiving p bits of the line code, and the second p gates receiving the logic inverses of p bits of the line code. A memory in the form of an integrated circuit comprises a planar memory array with memory cells accessible by a group of bit lines and a group of word lines, a decoder of bit lines (COLDEC) and a decoder of word lines (ROWDEC).
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公开(公告)号：FR2799043B1
公开(公告)日：2001-12-14
申请号：FR9912149
申请日：1999-09-29
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , BERTRAND BERTRAND , NAURA DAVID
Abstract: The columns register of a memory in the form of integrated circuit is of EEPROM technology type, and the method for writing a data word with 2p bits, where p is an integer, comprises the following steps: (i) erasing all cells of the word; (ii) loading 2q data to the same number of high-voltage latches (HV1,HV3,HV5,HV7), and loading 2p-2q other data to that number of low-voltage latches (LV0,LV2,LV4,LV6); (iii) programming 2q cells of the words memory (M0,M2,M4,M6) as a function of stored data in the high-voltage latches; and the following steps repeated 2p-q-1 times: (iv) loading 2q other data in the high-voltage latches, which were loaded to the low-voltage latches in step (ii); and (v) programming 2q other cells of the words memory (M1,M3,M5,M7) as a function of data stored in the high-voltage latches. The columns register comprises 2q high-voltage latches, where q is an integer strictly less than p, where each high-voltage latch comprises the means for high voltage storage for the storage of a binary datum, as high programming voltage, e.g. 18 V, or zero voltage, coupled to the mean for conditional and selective switching for carrying the high programming voltage to the determined bit line; and 2p-q low-voltage latches, where each low-voltage latch comprises the means for low voltage storage for the storage of a binary datum as low supply voltage, e.g. 5 V, or zero voltage, and thee means for coupling to the input of one of the high-voltage latches, which is activated for loading the binary datum stored in the low-voltage latch. In particular, the integer p = 3, and q = 2. The means for conditional and selective switching comprise a MOS transistor with n-type conductivity channel, connected by the gate to the output of high-voltage storage means, by the drain to high programming voltage, and to the bit lines (BL0,BL1) by the intermediary of MOS transistors for the purpose of insulation of the bit lines in the read mode and the selection of particular bit line in the write mode. The first and second loading means share at least one loading transistor (TC1,TC2), which are activated simultaneously by at least first loading signal (LOAD1,LOAD2) applied to the gate of loading transistor, connected to a transistor for word selection (TS1) with the gate receiving the word selection signal (COL). The means for high voltage storage in the high-voltage latches comprise two inverters in CMOS technology in antiparallel connection between the high programming voltage and the ground, and the means for low voltage storage comprise analogous components connected between the low supply voltage and the ground. An integrated circuit memory comprises a planar memory with at least 2p cells connected to the respective bit lines, and proposed columns register. A memory comprises several words memory on the same line, and the means for writing to certain or all of words memory simultaneously. The programming step (v) is followed by a step (vi) for bringing to zero the means for storage of low-voltage and high-voltage latches. The steps (i) and/or (iii) to (v) are operated simultaneously for several or all of words memory of the same line of memory cells.
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公开(公告)号：DE69801143D1
公开(公告)日：2001-08-23
申请号：DE69801143
申请日：1998-10-12
Applicant: ST MICROELECTRONICS SA
Inventor： NAURA DAVID , ZINK SEBASTIEN
Abstract: The floating grid memory has a high-tension generating circuit for memory programming/erasure with a charge pump for producing a pumped voltage and shaping circuit (2) for supplying a programming or erasing voltage from the pumped voltage. The circuit has control components (5,6,104) to provide control signal (SC) and a commutation circuit (7) to provide a commutated voltage equal to the pumped voltage or a neutral voltage according to the control signal fed to the shaping circuit.
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公开(公告)号：FR2799043A1
公开(公告)日：2001-03-30
申请号：FR9912149
申请日：1999-09-29
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , BERTRAND BERTRAND , NAURA DAVID
Abstract: The columns register of a memory in the form of integrated circuit is of EEPROM technology type, and the method for writing a data word with 2p bits, where p is an integer, comprises the following steps: (i) erasing all cells of the word; (ii) loading 2q data to the same number of high-voltage latches (HV1,HV3,HV5,HV7), and loading 2p-2q other data to that number of low-voltage latches (LV0,LV2,LV4,LV6); (iii) programming 2q cells of the words memory (M0,M2,M4,M6) as a function of stored data in the high-voltage latches; and the following steps repeated 2p-q-1 times: (iv) loading 2q other data in the high-voltage latches, which were loaded to the low-voltage latches in step (ii); and (v) programming 2q other cells of the words memory (M1,M3,M5,M7) as a function of data stored in the high-voltage latches. The columns register comprises 2q high-voltage latches, where q is an integer strictly less than p, where each high-voltage latch comprises the means for high voltage storage for the storage of a binary datum, as high programming voltage, e.g. 18 V, or zero voltage, coupled to the mean for conditional and selective switching for carrying the high programming voltage to the determined bit line; and 2p-q low-voltage latches, where each low-voltage latch comprises the means for low voltage storage for the storage of a binary datum as low supply voltage, e.g. 5 V, or zero voltage, and thee means for coupling to the input of one of the high-voltage latches, which is activated for loading the binary datum stored in the low-voltage latch. In particular, the integer p = 3, and q = 2. The means for conditional and selective switching comprise a MOS transistor with n-type conductivity channel, connected by the gate to the output of high-voltage storage means, by the drain to high programming voltage, and to the bit lines (BL0,BL1) by the intermediary of MOS transistors for the purpose of insulation of the bit lines in the read mode and the selection of particular bit line in the write mode. The first and second loading means share at least one loading transistor (TC1,TC2), which are activated simultaneously by at least first loading signal (LOAD1,LOAD2) applied to the gate of loading transistor, connected to a transistor for word selection (TS1) with the gate receiving the word selection signal (COL). The means for high voltage storage in the high-voltage latches comprise two inverters in CMOS technology in antiparallel connection between the high programming voltage and the ground, and the means for low voltage storage comprise analogous components connected between the low supply voltage and the ground. An integrated circuit memory comprises a planar memory with at least 2p cells connected to the respective bit lines, and proposed columns register. A memory comprises several words memory on the same line, and the means for writing to certain or all of words memory simultaneously. The programming step (v) is followed by a step (vi) for bringing to zero the means for storage of low-voltage and high-voltage latches. The steps (i) and/or (iii) to (v) are operated simultaneously for several or all of words memory of the same line of memory cells.
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公开(公告)号：DE69800399T2
公开(公告)日：2001-03-15
申请号：DE69800399
申请日：1998-09-10
Applicant: ST MICROELECTRONICS SA
Inventor： NAURA DAVID , ZINK SEBASTIEN
Abstract: The method involves optimizing the voltage slope of the programming ramp dependent on the memory cell number.
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Patent Agency Ranking
公开(公告)号：DE69800399D1
公开(公告)日：2000-12-21
申请号：DE69800399
申请日：1998-09-10
Applicant: ST MICROELECTRONICS SA
Inventor： NAURA DAVID , ZINK SEBASTIEN
Abstract: The method involves optimizing the voltage slope of the programming ramp dependent on the memory cell number.
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公开(公告)号：DE602004012923T2
公开(公告)日：2009-06-04
申请号：DE602004012923
申请日：2004-05-26
Applicant: ST MICROELECTRONICS SA
Inventor： LECONTE BRUNO , CAVALERI PAOLA , ZINK SEBASTIEN
IPC: G11C16/10
Abstract: The memory has a sequencer (SEQ2) to store sequence of external words in a buffer memory (BMEM2). The sequencer stores internal words present in the page in the buffer memory, erases the page and stores words present in the buffer memory in the erased page. The page is formed by memory cell in a main memory (FMEM2). The buffer memory has the external words and the internal words. An independent claim is also included for a method for storing sequence of external words in a target page of a main memory.
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公开(公告)号：DE60133513D1
公开(公告)日：2008-05-21
申请号：DE60133513
申请日：2001-02-05
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , CAVALERI PAOLA , LECONTE BRUNO
Abstract: A serial input/output memory is able to read data in the memory upon reception of a partial read address in which there are N least significant bits lacking to form a complete address. The read-ahead step includes: simultaneously reading the P first bits of M words of the memory having the same partial address; when the received address is complete, selecting the P first bits of the word designated by the complete address and delivering these bits at the serial output of the memory; reading P following bits of the word designated by the complete address during the delivery of P previous bits and delivering these bits at the serial output of the memory when the P previous bits are delivered.
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公开(公告)号：FR2863764A1
公开(公告)日：2005-06-17
申请号：FR0314622
申请日：2003-12-12
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , CAVALERI PAOLA , LECONTE BRUNO
Abstract: The memory (MEM) has a comparator, an output buffer, and a central unit preventing execution of read or write command if high order address of extended address is different from that of high order address allocated to the memory. The buffer, the unit and the comparator are arranged to allow the memory to effectuate reading of a plane memory (MA) while preventing data read in the memory (MA) from being applied on serial input/output. An independent claim is also included for a method of manufacturing a plane memory addressable with an extended address.
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公开(公告)号：DE60109958D1
公开(公告)日：2005-05-12
申请号：DE60109958
申请日：2001-11-14
Applicant: ST MICROELECTRONICS SA
Inventor： CAVALERI PAOLA , LECONTE BRUNO , ZINK SEBASTIEN , DEVIN JEAN
Abstract: The present invention relates to a page-erasable FLASH memory including a memory array having a plurality of pages each with floating-gate transistors connected by their gates to word lines, a word line decoder connected to the word lines of the memory, and the application of a positive erase voltage to the source or drain electrodes of all the floating-gate transistors of a sector forming a page to be erased. According to the present invention, the word line decoder includes a unit for applying, when a page is being erased, a negative erase voltage to the gates of the transistors of the page to be erased, while applying a positive inhibit voltage to the gates of the transistors of at least one page that is not to be erased.
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