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    21.
    发明专利
    未知

    公开(公告)号：DE60032113D1

    公开(公告)日：2007-01-11

    申请号：DE60032113

    申请日：2000-02-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MASTROMATTEO UBALDO ,  VILLA FLAVIO ,  BARLOCCHI GABRIELE

    IPC: B01L7/00 ,  A01G9/02 ,  B01J19/00 ,  B01L3/00 ,  B26D1/24 ,  B29C53/04 ,  B29C61/02 ,  B32B3/28 ,  B32B7/02 ,  B32B37/14 ,  B44C3/04 ,  B44C3/08 ,  B44C5/06 ,  B44F1/14

    Abstract: The integrated device (1) for microfluid thermoregulation comprises a semiconductor material body (2) having a surface (3); a plurality of buried channels (4) extending in the semiconductor material body (2) at a distance from the surface (3) of the semiconductor material body (2); inlet and outlet ports (5a, 5b) extending from the surface (3) of the semiconductor material body (2) as far as the ends (4a, 4b) of the buried channels (4) and being in fluid connection with the buried channels; and heating elements (10) on the semiconductor material body. Temperature sensors (15) are arranged between the heating elements (10) above the surface (3) of the semiconductor material body (2).

    22.
    发明专利
    未知

    公开(公告)号：DE69930099D1

    公开(公告)日：2006-04-27

    申请号：DE69930099

    申请日：1999-04-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BARLOCCHI GABRIELE ,  VILLA FLAVIO

    IPC: H01L21/764 ,  H01L21/20 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762

    Abstract: The method allows formation of buried cavities in a wafer (25) of monocrystalline semiconductor material. Initially, at least one cavity (21) is formed in a substrate (10) of monocrystalline semiconductor material, by timed TMAH etching silicon, then the cavity is covered with a material inhibiting epitaxial growth (22); finally, a monocrystalline epitaxial layer (26) is grown above the substrate (10) and the cavities (21). Thereby, the cavity (21) is completely surrounded by monocrystalline material. Starting from this wafer, it is possible to form a thin membrane (52). The original wafer (25) must have a plurality of elongate cavities or channels (21), parallel and adjacent to one another. Trenches (44) are then excavated in the epitaxial layer (26), as far as the channels (21), and the dividers between the channels are removed by timed TMAH etching.

    26.
    发明专利
    未知

    公开(公告)号：DE69841104D1

    公开(公告)日：2009-10-08

    申请号：DE69841104

    申请日：1998-12-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BARLOCCHI GABRIELE ,  VILLA FLAVIO

    IPC: H01L21/301 ,  H01L21/762 ,  H01L27/12

    Abstract: The method comprises the steps of: on a wafer (1) of monocrystalline semiconductor material, forming a hard mask (9) of an oxidation-resistant material, defining first protective regions (7) covering first portions (21) of the wafer (1); excavating the second portions (8'') of the wafer (1), forming initial trenches (10) extending between the first portions (8') of the wafer (1); thermally oxidating the wafer (1), forming a sacrificial oxide layer (14) extending at the lateral and base walls (10a, 10b) of the initial trenches (10), below the first protective regions (7); and wet etching the wafer (1), to completely remove the sacrificial oxide layer (14). Thereby, intermediate trenches (10') are formed, the lateral walls (10a') of which are recessed with respect to the first protective regions (7). Subsequently, a second oxide layer 11 is formed inside the intermediate trenches 10'; a second silicon nitride layer 12 is deposited; final trenches 16 are produced; a buried oxide region 22 is formed, and finally an epitaxial layer 23 is grown.

    27.
    发明专利
    未知

    公开(公告)号：DE69935495D1

    公开(公告)日：2007-04-26

    申请号：DE69935495

    申请日：1999-04-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BARLOCCHI GABRIELE ,  VILLA FLAVIO ,  CORONA PIETRO

    IPC: H01L21/764 ,  B01L3/00 ,  B81C1/00 ,  H01L21/20

    Abstract: The process comprises the steps of forming, on a monocrystalline-silicon body (11), an etching-aid region (13) of polycrystalline silicon; forming, on the etching-aid region (13), a nucleus region (17) of polycrystalline silicon, surrounded by a protective structure (26) having an opening (22') extending as far as the etching-aid region (13); TMAH-etching the etching-aid region (13) and the monocrystalline body (11), forming a tub shaped cavity (30); removing the top layer (19) of the protective structure (26); and growing an epitaxial layer (33) on the monocrystalline body (11) and the nucleus region (17). The epitaxial layer, of monocrystalline type (33a) on the monocrystalline body (11) and of polycrystalline type (33b) on the nucleus region (17), closes upwardly the etching opening (22'), and the cavity (30) is thus completely embedded in the resulting wafer (34).

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