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    21.
    发明专利
    未知

    公开(公告)号：DE60024246T2

    公开(公告)日：2006-08-10

    申请号：DE60024246

    申请日：2000-06-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： COLONNA VITTORIO ,  BASCHIROTTO ANDREA ,  CUSINATO PAOLO ,  GANDOLFI GABRIELE

    IPC: H03F3/45

    Abstract: The present invention refers to a completely differential operational amplifier of the folded cascode type. In one embodiment the completely differential operational amplifier of the folded cascode type comprises: a differential output stage (15, 16, 17, 18, 19, 20 21, 22); a differential input stage (11, 12) able to drive said output stage (15, 16, 17, 18, 19, 20 21, 22); said differential output stage (15, 16, 17, 18, 19, 20 21, 22) includes a first branch (15, 16, 17, 18) having at least a first (16) and a second (17) transistor, and a second branch (19, 20 21, 22) having at least a third (20) and a fourth (21) transistor; said first (15, 16, 17, 18) and second (19, 20 21, 22) branch are coupled to a first (VDD) and to a second (GND) feeding voltage; a feedback circuit (40) of said first (16), second (17), third (20) and fourth (21) transistors; characterized in that said feedback circuit (40) is constituted by a single amplifier (40) having four inputs (IN1, IN2, IN3, IN4) and four outputs (OUT1, OUT2, OUTS, OUT4), said four inputs (IN1, IN2, IN3, IN4) take the voltage present on a terminal (23, 13, 24, 14) of said first (16), second (17), third (20) and fourth (21) transistors, and said four outputs (OUT1, OUT2, OUT3, OUT4) provide each a voltage to the control elements of said first (16), second (17), third (20) and fourth (21) transistors, which depend on the value of the input voltage of said four inputs (IN1, IN2, IN3, IN4).

    23.
    发明专利
    未知

    公开(公告)号：DE60018557D1

    公开(公告)日：2005-04-14

    申请号：DE60018557

    申请日：2000-07-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GANDOLFI GABRIELE ,  BASCHIROTTO ANDREA ,  COLONNA VITTORIO ,  CUSINATO PAOLO

    IPC: H03M3/02

    Abstract: The present invention refers to a digital analogical converter comprising a sigma delta cascade modulator having two outputs, particularly a third order sigma delta modulator 2+1. In an embodiment the digital analogical converter comprises: a sigma delta modulator (1) of the type having two outputs (67, 68) able to supply a first (Y1) and a second (Y2) signal to said two outputs (67, 68); a reconstruction circuit (2) of first said (Y1) and second (Y2) signal able to provide a reconstructed signal (Yout); a filter (3) able to filter said reconstructed signal (Yout); characterized in that said reconstruction circuit (2) combines said first (Y1) and second (Y2) signals according to the following relationship Yout= Y1* (1+ Z ) - Y2* (1- Z ) + Y2* Z * (1- Z ) where Yout corresponds to said reconstructed signal, Y1 corresponds to said first signal, Y2 corresponds to said according to signal, Z corresponds to the Z transform.

    24.
    发明专利
    未知

    公开(公告)号：IT1315978B1

    公开(公告)日：2003-03-26

    申请号：ITRM20000425

    申请日：2000-07-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CUSINATO PAOLO ,  BASCHIROTTO ANDREA ,  PASOLINI FABIO

    IPC: H03M3/00

    Abstract: A method of re-establishing the stability of a sigma-delta modulator having a plurality of integrator stages in cascade and a quantizer, achieving very short resetting times, a bit sequence corresponding to an instability state of the modulator is defined, the bit-stream output by the modulator is monitored to check whether it includes the instability sequence and, if the instability sequence is detected, the last integrator stage is reset and one or more preceding integrator stages are reset, progressively, until the instability sequence is no longer detected.

    25.
    发明专利
    未知

    公开(公告)号：DE69623963D1

    公开(公告)日：2002-10-31

    申请号：DE69623963

    申请日：1996-10-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BASCHIROTTO ANDREA ,  NAGARI ANGELO ,  CASTELLO RINALDO

    IPC: H03F3/00 ,  H03F3/45 ,  H03H1/00

    Abstract: In switch-capacitor systems for extremely low supply voltage, employing fully differential switched op-amp, proper functioning of nMOS switches coupled to the inverting input node of an integrated stage capable of outputting a common mode control signal, is may possible by retaining the ground potential on the input node to prevent body effects on the threshold of nMOS switches by means of an auxiliary switched capacitor.

    26.
    发明专利
    未知

    公开(公告)号：ITMI20020459D0

    公开(公告)日：2002-03-06

    申请号：ITMI20020459

    申请日：2002-03-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BASCHIROTTO ANDREA ,  GANDOLFI GABRIELE ,  COLONNA VITTORIO

    IPC: H03M3/00

    Abstract: A sigma-delta-type converter comprises: a sigma-delta modulator having a digital output having a first prefixed bit number; a randomizer including a circular memory; an analogical reconstruction filter comprising a branch number equal to said first default number including sampling capacitors and a low-pass filter; characterized in that said circular memory comprises a number of elements equal to said first default number of bits less one and receives in input said first default number of bits less one, and in that a bit of said first default number of bits is applied to one of said branches of said reconstruction filter.

    28.
    发明专利
    未知

    公开(公告)号：ITRM20000425D0

    公开(公告)日：2000-07-31

    申请号：ITRM20000425

    申请日：2000-07-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CUSINATO PAOLO ,  BASCHIROTTO ANDREA ,  PASOLINI FABIO

    IPC: H03M3/00

    Abstract: A method of re-establishing the stability of a sigma-delta modulator having a plurality of integrator stages in cascade and a quantizer, achieving very short resetting times, a bit sequence corresponding to an instability state of the modulator is defined, the bit-stream output by the modulator is monitored to check whether it includes the instability sequence and, if the instability sequence is detected, the last integrator stage is reset and one or more preceding integrator stages are reset, progressively, until the instability sequence is no longer detected.

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