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    22.
    发明专利
    未知

    公开(公告)号：ITMI981376A1

    公开(公告)日：1999-12-16

    申请号：ITMI981376

    申请日：1998-06-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PINTO ANGELO ,  PALARA SERGIO

    IPC: H01L21/265 ,  H01L21/331

    Abstract: The method comprises forming an implantation screening layer of predetermined thickness on the wafer, forming, in the screening layer, a first rectilinear, elongate opening having a first width, and at least a second rectilinear, elongate opening substantially parallel to the first opening and having a second width smaller than the first width is formed on the screening layer. The wafer is then subjected to ion implantation with two ion beams directed in directions substantially perpendicular to the longitudinal axes of the openings and inclined to the surface of the wafer at predetermined angles so as to strike the openings from two opposite sides. The thickness of the screening layer, the widths of the openings, and the angles of inclination of the ion beams being selected in a manner such that the beams strike the base of the first opening for substantially uniform doping of the underlying area of the wafer, but do not strike the base of the second opening. The novel method and apparatus enables selective doping by ion implantation to be performed without the use of a mask which is otherwise necessary for screening the second opening.

    26.
    发明专利
    未知

    公开(公告)号：IT1236797B

    公开(公告)日：1993-04-02

    申请号：IT2242889

    申请日：1989-11-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FERLA GIUSEPPE ,  PALARA SERGIO

    IPC: H01L21/331 ,  H01L29/73 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/082 ,  H01L29/732 ,  H01L

    Abstract: The monolithic vertical-type semiconductor power device comprises an N+ type substrate (1) over which there is superimposed an N- type epitaxial layer (2) in which there is obtained aP type insulation pocket (3). Such pocket contains N type regions (4, 15) and P type regions (8) which in turn contain N+ type regions (11, 12; 13; 14) and of P type regions (6, 7, 9, 10) which define circuit components (T1, T2, T5) of the device. Insulation pocket (3) is wholly covered by a first metallisation (21, 30) connected to ground. Such metallisation (21, 30) is in turn protected by a layer of insulating material (18) suitable for allowing the crossing of metal tracks (20) or of a second metallisation (31) for the connection of the different components.

    27.
    发明专利
    未知

    公开(公告)号：DE69533391D1

    公开(公告)日：2004-09-23

    申请号：DE69533391

    申请日：1995-04-28

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： PALARA SERGIO ,  SUERI STEFANO ,  SCHIACCIANOCE SALVATORE

    IPC: G01R19/165 ,  F02P17/12 ,  G01R29/027 ,  H01T13/60 ,  H02H3/08 ,  H02H3/20 ,  G01R31/38

    Abstract: The invention relates to a circuit for detecting an overvoltage in an electrical load (Z1) inserted with a first and a second terminal between a feed line (AL) and a control switch (S), the circuit having an output voltage (Vout) at an output terminal (OUT) and comprising: at least one first threshold comparator (C1) having a first input terminal held at a first reference voltage (E1), a second input terminal connected to the feed line (AL) and an output terminal, at least one second threshold comparator (C2) having a first input terminal held at a second reference voltage (E2), a second input terminal connected to a second terminal of the electrical load (Z1), and an output terminal, at least one output transistor (T1) inserted with a first and a second terminal between the feed line (AL) and an output terminal (OUT) of the circuit (1), the transistor (T1) being controlled by at least one logic block (D) having inputs connected to the outputs of the threshold comparators (C1) and (C2), at least one feedback block (R) inserted with an input terminal and an output terminal respectively between the output terminal (OUT) of circuit (1) and a further input terminal to the logic block (D).

    28.
    发明专利
    未知

    公开(公告)号：DE69530077T2

    公开(公告)日：2003-11-27

    申请号：DE69530077

    申请日：1995-07-31

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： PALARA SERGIO ,  GRAZIANO VITO

    IPC: H02M7/5383 ,  H03K17/16 ,  H03K17/284 ,  H05B41/282 ,  H05B41/00 ,  H03K17/687 ,  H05B41/295

    Abstract: The principle on which the start up circuit of this invention operates is that of causing the MOS transistor (M2) to be turned on by sensing local electrical quantities thereof, specifically the potential at the drain terminal (D) of the MOS transistor (M2). The basic idea is to inject a small current into the control terminal (G) when the potential at the drain terminal (D) is high. For the purpose, an electric network (SN) is arranged to couple these two terminals together.

    29.
    发明专利
    未知

    公开(公告)号：DE69525048D1

    公开(公告)日：2002-02-21

    申请号：DE69525048

    申请日：1995-07-27

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： LEONARDI SALVATORE ,  LIZZIO PIETRO ,  PATTI DAVIDE GIUSEPPE ,  PALARA SERGIO

    IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732

    Abstract: A vertical PNP transistor integrated in a semiconductor material wafer having an N type substrate (40) and an N type epitaxial layer (41) forming a surface (42). The transistor has a P type buried collector region (43) astride the substrate and the epitaxial layer; a collector sinker (44) insulating an epitaxial tub (45) from the rest of the wafer; a gain-modulating N type buried base region (46; 46'; 46'') astride the buried collector region and the epitaxial tub, and forming a base region with the epitaxial tub; and a P type emitter region in the epitaxial tub. An N type base sinker (47) extends from the surface, through the epitaxial tub to the buried base region. The gain of the transistor may be modulated by varying the extension and dope concentration of the buried base region (46), forming a constant or variable dope concentration profile of the buried base region (46), providing or not a base sinker (47), and varying the form and distance of the base sinker from the emitter region.

    30.
    发明专利
    未知

    公开(公告)号：IT1301729B1

    公开(公告)日：2000-07-07

    申请号：ITMI981376

    申请日：1998-06-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PINTO ANGELO ,  PALARA SERGIO

    IPC: H01L21/265 ,  H01L21/331

    Abstract: The method comprises forming an implantation screening layer of predetermined thickness on the wafer, forming, in the screening layer, a first rectilinear, elongate opening having a first width, and at least a second rectilinear, elongate opening substantially parallel to the first opening and having a second width smaller than the first width is formed on the screening layer. The wafer is then subjected to ion implantation with two ion beams directed in directions substantially perpendicular to the longitudinal axes of the openings and inclined to the surface of the wafer at predetermined angles so as to strike the openings from two opposite sides. The thickness of the screening layer, the widths of the openings, and the angles of inclination of the ion beams being selected in a manner such that the beams strike the base of the first opening for substantially uniform doping of the underlying area of the wafer, but do not strike the base of the second opening. The novel method and apparatus enables selective doping by ion implantation to be performed without the use of a mask which is otherwise necessary for screening the second opening.

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