公开(公告)号：DE69228812D1

公开(公告)日：1999-05-06

申请号：DE69228812

申请日：1992-09-14

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO

IPC: H03F3/343 ,  H03F3/347 ,  H03H11/48 ,  H04B1/58 ,  H04M1/58 ,  H04M1/76 ,  H04M1/00

Abstract: The invention relates to a method for implementing an impedance associated with a monolithically integrated telephone subscriber circuit (2) which is connected to a telephone line (3) having at least one terminal pair (L+,L-). The method consists of providing, a single resistor (Re) connected serially to one terminal (L+) of the telephone line (3), and circuit means (1) connected in a closed loop to the terminal (L+) to divide, by a predetermined factor, the value of the resistor (Re) on the occurrence of DC or very low frequency signals.

公开(公告)号：DE69228420D1

公开(公告)日：1999-03-25

申请号：DE69228420

申请日：1992-09-16

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO

IPC: H04M19/08

Abstract: A certain amount of DC supply current derivable from a subscriber's line (VL, GROUND) is used for powering at respective regulated voltages a plurality of functional circuits (A,B...) of an equipment connectable to the line. A sensible energy saving can be achieved by splitting the valuable current among the functional circuits, on account of their priority rank, by using at least a differential pair of current delivering transistors (P2,P3). A special circuit monitors the actual current of absorption of the functional circuit of highest rank (A) and produces a control signal that is used for modifying the drive conditions of the current delivering transistors. The current waste caused by sinking a design maximum current through a dissipative shunt voltage regulator of each functional circuit as done in the prior art circuits, is prevented and all the current exceeding the actual absorption needs of the highest rank functional circuit may be distributed to the other functional circuits without waste. This same principle may be advantageously applied also to functional circuits of lesser and lesser rank of priority for maximizing the saving.

公开(公告)号：DE69224467T2

公开(公告)日：1998-06-10

申请号：DE69224467

申请日：1992-09-15

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO

IPC: H04M20060101 ,  H04M1/00 ,  H04M1/60 ,  H04M1/76 ,  H04M19/08

Abstract: A circuit is described which comprises an operational amplifier A, two resistors R1, R2, connected between the telephone line L and the inputs of the amplifier, a capacitor C, which is charged by a first bipolar transistor P1 controlled by the amplifier via a first FET transistor M1, a second bipolar transistor P2 arranged in parallel with the connection of the first transistor P1 and the capacitor C, a second FET transistor M2, equal to the first and with "source" and "gate" terminals connected to the corresponding terminals of the first one, and two current generators CC1, CC2, connected to the "drain" terminals, respectively, of the first and the second FET transistor and to the bases, respectively, of the first and the second bipolar transistor P1, P2. The currents I1, I2 of the two generators and the other parameters of the circuit are such as to keep the first and the second bipolar transistor respectively conducting and inhibited, except in the case when the line voltage drops below a minimum predetermined value: in such case, the first and the second transistor respectively switch to inhibition and conduction. The circuit has a lower "voltage loss" than the known circuits.

公开(公告)号：DE69223318T2

公开(公告)日：1998-03-19

申请号：DE69223318

申请日：1992-07-29

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO

IPC: H03F1/34 ,  H03H7/06 ,  H03H11/04 ,  H03H11/12 ,  H04M1/00

公开(公告)号：DE60123223D1

公开(公告)日：2006-11-02

申请号：DE60123223

申请日：2001-06-28

Applicant: ST MICROELECTRONICS SRL

Inventor： GUINEA JESUS ,  TOMASINI LUCIANO

IPC: H03L7/081

Abstract: The present invention relates a circuit for generating a digital output signal (56) locked to a phase of an input signal (24), comprising a plurality of delay cells (42), a first register (31) containing a first value, a phase detector (26) and a control logic (25), which is characterized by comprising a plurality of flip - flop devices (37, ..., 38), wherein storing said first value, a second register (30) containing a second value, a plurality of adder nodes (33) adapted to sum in each of said delay cells (42) said second value with the content of said selected flip - flop device (37, ..., 38), being said delay cells (42) adapted to provide said digital output signal (56), said phase detector (26), receiving said input signal (24) and said digital output signal (56), adapted to detect the phase difference (27) between said input signal and said digital output signal (56), said control logic (25) adapted to control said first and second value in function of said phase difference (27).

公开(公告)号：DE60030836D1

公开(公告)日：2006-11-02

申请号：DE60030836

申请日：2000-02-22

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CLERICI GIANCARLO

IPC: H04M19/08 ,  H04M1/74

公开(公告)号：DE69922811D1

公开(公告)日：2005-01-27

申请号：DE69922811

申请日：1999-10-21

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  GUINEA JESUS

IPC: H03F1/30 ,  H03F3/30

公开(公告)号：DE69529828D1

公开(公告)日：2003-04-10

申请号：DE69529828

申请日：1995-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  CLERICI GIANCARLO ,  BIETTI IVAN

IPC: H03F1/08 ,  H03F1/00

Abstract: An operational amplifier (5) with adjustable frequency compensation comprises a transconductance input stage (2) and an amplifier output stage (3) connected serially together between an input terminal (IN) and an output terminal (OUT) of the operational amplifier. At least one compensation block (6) is connected across the input and the output of said output stage (3), According to the invention, the compensation block (6) comprises a plurality (N) of charge storage elements (CCn) connected in parallel together and in series to a switch block (7) which selectively connects a sub-plurality (N') of said charge storage elements (CCn) across the input and the output of said output stage (3) on the basis of an external signal (SEL) of the amplifier (5).

公开(公告)号：DE69229734T2

公开(公告)日：2000-03-02

申请号：DE69229734

申请日：1992-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO

IPC: H03H7/06 ,  H03H7/00 ,  H03H11/34 ,  H03H11/36 ,  H04M1/60 ,  H04M1/76

Abstract: A monolithically integrated AC coupler comprising two capacitors, C1 and C2, respectively connected between an input terminal Vin and an output terminal Vout, and between one said output terminal and a first terminal of connection to a reference potential Vref1. Connected in parallel with the capacitor C1, and serially together, are a capacitor C3 and two field-effect transistors, M1 and M2. Two field-effect transistors, M3 and M4, are connected between the output terminal and a second terminal of connection to a reference potential, Vref2. The connection nodes between the transistors M1 and M2 and between the transistors M3 and M4 are coupled, through two capacitors CS1 and CS2, to the first connection terminal Vref1. The gate terminals of the transistors are applied control signals with two non-overlapping phases, F1 and F2.

公开(公告)号：ITRM20000032D0

公开(公告)日：2000-01-20

申请号：ITRM20000032

申请日：2000-01-20

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  GUINEA JESUS ,  CASTELLO RINALDO

IPC: G05F3/24 ,  G05F3/26

Abstract: The generator includes complementary MOS transistors interconnected in four circuit branches one of which contains a constant-current generator. Voltages picked up at various nodes of the circuit can be used as reference and/or biasing voltages of the integrated circuit, which account for the variability of the manufacturing parameters.