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    21.
    发明专利
    未知

    公开(公告)号：DE69631524D1

    公开(公告)日：2004-03-18

    申请号：DE69631524

    申请日：1996-07-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MAGRI ANGELO ,  ZAMBRANO RAFFAELE ,  FRISINA FERRUCCIO

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

    Abstract: A MOS technology power device comprises a semiconductor substrate (1), a semiconductor layer (2) of a first conductivity type superimposed over the semiconductor substrate (1), an insulated gate layer (5,6,7;51,52,6,7) covering the semiconductor layer (2), a plurality of substantially rectilinear elongated openings (10) parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes (3) of a second conductivity type formed in the semiconductor layer (2) under the elongated openings (10), source regions (4) of the first conductivity type included in the body stripes (3) and a metal layer (9) covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings. Each body stripe comprises first portions (31) substantially aligned with a first edge of the respective elongated opening and extending under a second edge of the elongated opening to form a channel region, each first portion (31) including a source region (4) extending substantially from a longitudinal axis of symmetry of the respective elongated opening to the second edge of the elongated opening, and second portions (32), longitudinally intercalated with the first portions (31), substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from the longitudinal axis of symmetry to the first edge of the elongated opening, the first portions (31) and second portions (32) of the body stripes (3) being respectively aligned in a direction transversal to the longitudinal axis.

    22.
    发明专利
    未知

    公开(公告)号：ITMI992350A1

    公开(公告)日：2001-05-10

    申请号：ITMI992350

    申请日：1999-11-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZAMBRANO RAFFAELE

    IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115

    Abstract: A process for selectively sealing ferroelectric capacitive elements in non-volatile memory cells being integrated in a semiconductor substrate and comprising at least one MOS transistor, which process comprises at least the following steps: forming said at least one MOS transistor on the semiconductor substrate, and depositing an insulating layer over the whole surface of the semiconductor; and further comprises the steps of: depositing a first metal layer to form, using a photolithographic technique, a lower electrode of at least one ferroelectric capacitive element; depositing a layer of a dielectric material onto said first layer; depositing a second metal layer to form, using a photolithographic technique, an upper electrode of at least one ferroelectric capacitive element; depositing a layer of a sealing material onto said second metal layer; defining the dielectric material layer and sealing layer by a single photolithographic defining step, so as to pattern said dielectric layer and concurrently seal said at least one capacitive element.

    23.
    发明专利
    未知

    公开(公告)号：ITMI990919A1

    公开(公告)日：2000-10-30

    申请号：ITMI990919

    申请日：1999-04-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZAMBRANO RAFFAELE ,  CORVASCE CHIARA

    IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/115

    Abstract: Presented is a ferroelectric non-volatile memory cell in a semiconductor substrate that has a MOS device connected in parallel to a ferroelectric capacitor. The MOS device has first and second conduction terminals and is covered with an insulating layer. The ferroelectric capacitor has a lower electrode formed on the insulating layer above the first conduction terminals and are electrically coupled to them. The lower electrode of the ferroelectric capacitor is covered with a layer of ferroelectric material and coupled capacitively to an upper electrode. The upper electrode is formed above the second conduction terminals and are electrically connected thereto, and extends over the ferroelectric material to at least partially overlap the lower electrode. Also presented is a non-volatile memory matrix that includes a plurality of the ferroelectric memory cells that are organized into rows and columns.

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