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    23.
    发明专利
    未知

    公开(公告)号：DE69421075T2

    公开(公告)日：2000-03-02

    申请号：DE69421075

    申请日：1994-06-10

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： BONTEMPO GREGORIO ,  PULVIRENTI FRANCESCO ,  COLLETTI PAOLO ,  GARIBOLDI ROBERTO

    IPC: H02H3/08 ,  H03K17/082 ,  H03K17/284

    Abstract: The invention relates to a non-dissipative device for protecting against overloading an integrated circuit having multiple independent channels, being of the type which comprises an input terminal (IN) and an output terminal (OUT) having an integrated switch (1) connected therebetween which consists of a first or input portion (2), a logic gate (PL1) with two inputs (I3,I4) a second or control portion (3), and a third or output portion (4), all in series with one another. The device further comprises a circuit (A) for generating the on- and off-times (Ton,Toff) of the integrated switch (1) connected between an output (O4) of the third portion (4) and an input terminal (I4) of said logic gate (PL1).

    25.
    发明专利
    未知

    公开(公告)号：DE69421075D1

    公开(公告)日：1999-11-11

    申请号：DE69421075

    申请日：1994-06-10

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： BONTEMPO GREGORIO ,  PULVIRENTI FRANCESCO ,  COLLETTI PAOLO ,  GARIBOLDI ROBERTO

    IPC: H02H3/08 ,  H03K17/082 ,  H03K17/284

    Abstract: The invention relates to a non-dissipative device for protecting against overloading an integrated circuit having multiple independent channels, being of the type which comprises an input terminal (IN) and an output terminal (OUT) having an integrated switch (1) connected therebetween which consists of a first or input portion (2), a logic gate (PL1) with two inputs (I3,I4) a second or control portion (3), and a third or output portion (4), all in series with one another. The device further comprises a circuit (A) for generating the on- and off-times (Ton,Toff) of the integrated switch (1) connected between an output (O4) of the third portion (4) and an input terminal (I4) of said logic gate (PL1).

    SYSTEM FOR DRIVING COLUMNS OF A LIQUID CRYSTAL DISPLAY
    27.
    发明申请
    SYSTEM FOR DRIVING COLUMNS OF A LIQUID CRYSTAL DISPLAY 审中-公开
    用于驱动液晶显示器的列的系统

    公开(公告)号：WO2004003882A8

    公开(公告)日：2004-06-03

    申请号：PCT/EP0306638

    申请日：2003-06-23

    Applicant: ST MICROELECTRONICS SRL ,  DORA SPA ,  PAPPALARDO SALVATORE ,  PULVIRENTI FRANCESCO ,  PRIVITERA SALVATORE ,  SALA LEONARDO

    Inventor： PAPPALARDO SALVATORE ,  PULVIRENTI FRANCESCO ,  PRIVITERA SALVATORE ,  SALA LEONARDO

    IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36

    CPC classification number: G09G3/3685 ,  G09G2330/021

    Abstract: The present invention refers to a system for driving columns of a liquid crystal display comprising a logic circuitry (10) operating in a supply path between a first (VDD) and a second (VSS) supply voltage in which the first supply voltage is (VDD) higher than the second supply voltage (VSS). The logic circuitry (10) is capable of generating starting from the first logic signals (LOW_FRAME, WHITE_PIX) in input second logic signals (CP, CN, CP_N, CN_N) in output whose value is equal to the first (VDD) or second (VSS) supply voltage. The device comprises two elevator devices (11, 12) coupled to the logic circuitry (10) and operating in a supply path between a third supply voltage (VLCD) greater than the first supply voltage (VDD) and the second supply voltage (VSS); the elevator devices (11, 12) are capable of raising the value of the second logic signals (CP, CN, CP_N, CN_N). The device also comprises a first (T11-T12) and a second (T13-T14) pair of transistors shaving different supply paths (VLCD-VA, VB-VSS) and having an output terminal (OUT) in common; the first (T11-T12) and the second (T13-T14) pair of transistors are connected to the elevator devices (11, 12) so as to determine the drive signal of a column. The device comprises turnoff circuitry (15) operating in a supply path between the third (VLCD) and the second supply voltage (VSS) and coupled to the two elevator devices (11, 12). The circuitry (15) is capable of keeping one of the two pairs of transistors (T11-T12, T13-T14) in a turnoff state in the period of time of a frame when the other of the two pairs of transistors (T11-T12, T13-T14) is in operative conditions.

    Abstract translation: 本发明涉及一种用于驱动液晶显示器的列的系统，其包括在第一（VDD）和第二（VSS）电源电压之间的供应路径中操作的逻辑电路（10），其中第一电源电压是VDD ）高于第二电源电压（VSS）。 逻辑电路（10）能够在输出中的输入第二逻辑信号（CP，CN，CP_N，CN_N）中的第一逻辑信号（LOW_FRAME，WHITE_PIX）开始产生，其输出值等于第一（VDD）或第二 VSS）电源电压。 该装置包括耦合到逻辑电路（10）并且在大于第一电源电压（VDD）的第三电源电压（VLCD）与第二电源电压（VSS）之间的电源路径中操作的两个电梯装置（11,12） ; 电梯设备（11,12）能够提高第二逻辑信号（CP，CN，CP_N，CN_N）的值。 该器件还包括一对共同提供不同电源路径（VLCD-VA，VB-VSS）并具有输出端（OUT）的第一（T11-T12）和第二（T13-T14） 第一（T11-T12）和第二（T13-T14）晶体管对连接到升降机装置（11,12）以确定列的驱动信号。 该装置包括在第三（VLCD）和第二电源电压（VSS）之间的供电路径中操作并耦合到两个电梯装置（11,12）的关断电路（15）。 当两个晶体管对（T11-T12）中的另一个晶体管（T11-T12）处于截止状态时，电路（15）能够保持两对晶体管（T11-T12，T13- ，T13-T14）处于操作状态。

    28.
    发明专利
    未知

    公开(公告)号：DE69732695D1

    公开(公告)日：2005-04-14

    申请号：DE69732695

    申请日：1997-07-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PULVIRENTI FRANCESCO ,  MILAZZO PATRIZIA

    IPC: G05F1/565

    Abstract: A linear type of voltage regulator, having at least one input terminal (VBAT) adapted to receive a supply voltage and one output terminal (VOUT) adapted to deliver a regulated output voltage, comprises a power transistor (M1) and a driver circuit for the transistor; the driver circuit comprises essentially an operational amplifier (OP1) having an input differential stage biased by a bias current which varies proportionally with the variations of the regulated output voltage at the output terminal (VOUT) of the regulator.

    29.
    发明专利
    未知

    公开(公告)号：DE69811674T2

    公开(公告)日：2004-04-29

    申请号：DE69811674

    申请日：1998-11-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PULVIRENTI FRANCESCO ,  BONTEMPO GREGORIO ,  PALUMBO GAETANO

    IPC: H04B3/54 ,  H02J13/00

    Abstract: A circuit for detecting signals present on a bifilar voltage-supply and signal-transmission line, in which the signals are constituted by positive and negative variations of the supply potential of at least one of the wires of the line (2), comprises: a low-pass filter (20) connected to the two wires of the line in order to supply, at an output terminal of the filter, a constant reference potential (V+) substantially equal to the supply potential of a preselected one of the two wires, a first threshold comparator (21) having a reference input terminal (27) and a threshold input terminal (29) connected, respectively, to the output terminal (18) of the filter (20) and to the preselected wire of the two wires, and a second threshold comparator (22) having a reference input terminal (28) and a threshold input terminal (30) connected, respectively, to the preselected wire of the two wires and to the output terminal (18) of the filter (20). The circuit is relatively simple, does not require synchronization signals, and can be formed as an integrated circuit, taking up a limited area.

    30.
    发明专利
    未知

    公开(公告)号：DE69808950D1

    公开(公告)日：2002-11-28

    申请号：DE69808950

    申请日：1998-12-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RIBELLINO CALOGERO ,  MILAZZO PATRIZIA ,  PULVIRENTI FRANCESCO

    IPC: H03K4/02 ,  H03K17/16

    Abstract: Integrated circuit (20, 80, 90) generating at least a voltage linear ramp having a slow rise of the type comprising an input terminal (21, 81, 91), connected to a first voltage reference (VREF) and an output terminal (24, 84, 94) adapted for providing a controlled ramp signal (VRAMP), the circuit comprising at least one operational amplifier (OP3) having a non-inverting input terminal connected to said input terminal (21, 81, 91) and to an output terminal in feedback on an inverting input terminal and connected to the output terminal (24, 84, 94) of the ramp generator circuit (20, 80, 90) itself. The ramp voltage generator (20, 80, 90) according to the invention further comprises a first storage capacitance (Cs) connected between the non-inverting input terminal of the operational amplifier (OP3) and a ground voltage reference (GND) and loaded by means of a second pumping capacitance (Cp) inserted in parallel to said first capacitance (Cs) between the input terminal (21, 81, 91) of the ramp generator circuit (20, 80, 90) and the ground voltage reference (GND).

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