公开(公告)号：IT8983626D0

公开(公告)日：1989-06-14

申请号：IT8362689

申请日：1989-06-14

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CONTIERO CLAUDIO ,  GALBIATI PAOLA ,  ZULLINO LUCIA

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/092 ,  H01L29/732 ,  H01L29/78

公开(公告)号：IT8423302D0

公开(公告)日：1984-10-25

申请号：IT2330284

申请日：1984-10-25

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CONTIERO CLAUDIO

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/336 ,  A61K

公开(公告)号：DE69410251D1

公开(公告)日：1998-06-18

申请号：DE69410251

申请日：1994-06-20

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： DIAZZI CLAUDIO ,  MURARI BRUNO ,  MASTROMATTEO UBALDO ,  CONTIERO CLAUDIO

IPC: H01L21/76 ,  H01L21/822 ,  H01L23/31 ,  H01L23/58 ,  H01L27/04

公开(公告)号：DE68925116T2

公开(公告)日：1996-05-09

申请号：DE68925116

申请日：1989-06-28

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CONTIERO CLAUDIO ,  GALBIATI PAOLA ,  ZULLINO LUCIA

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/82

Abstract: A high density, mixed technology integrated circuit comprises CMOS structures and bipolar lateral transistors, the electrical efficiency and Early voltage of which are maintained high by forming "well" regions through the collector area. The operation determines the formation of a "collector extension region" extending relatively deep within the epitaxial layer so as to intercept the emitter current and gather it to the collector, subtracting it from dispersion toward the substrate through the adjacent isolation junctions surrounding the region of the lateral bipolar transistor. Under comparable conditions, the ratio between Ic/Isubstrate is incremented from about 8 to about 300 and the Early voltage from about 20 V to about 100 V. The VCEO, BVCBO and BVCES voltages are also advantageously increased by the presence of said "well" region formed in the collector zone.

公开(公告)号：DE3751313T2

公开(公告)日：1996-02-01

申请号：DE3751313

申请日：1987-03-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： ANDREINI ANTONIO ,  CONTIERO CLAUDIO ,  GALBIATI PAOLA

IPC: H01L21/033 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L21/82

公开(公告)号：DE68925116D1

公开(公告)日：1996-01-25

申请号：DE68925116

申请日：1989-06-28

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CONTIERO CLAUDIO ,  GALBIATI PAOLA ,  ZULLINO LUCIA

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/82

Abstract: A high density, mixed technology integrated circuit comprises CMOS structures and bipolar lateral transistors, the electrical efficiency and Early voltage of which are maintained high by forming "well" regions through the collector area. The operation determines the formation of a "collector extension region" extending relatively deep within the epitaxial layer so as to intercept the emitter current and gather it to the collector, subtracting it from dispersion toward the substrate through the adjacent isolation junctions surrounding the region of the lateral bipolar transistor. Under comparable conditions, the ratio between Ic/Isubstrate is incremented from about 8 to about 300 and the Early voltage from about 20 V to about 100 V. The VCEO, BVCBO and BVCES voltages are also advantageously increased by the presence of said "well" region formed in the collector zone.

公开(公告)号：DE3751313D1

公开(公告)日：1995-06-29

申请号：DE3751313

申请日：1987-03-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： ANDREINI ANTONIO ,  CONTIERO CLAUDIO ,  GALBIATI PAOLA

IPC: H01L21/033 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L21/82

公开(公告)号：DE3587231T2

公开(公告)日：1993-07-08

申请号：DE3587231

申请日：1985-10-18

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CONTIERO CLAUDIO

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/336 ,  H01L29/08

公开(公告)号：DE3778961D1

公开(公告)日：1992-06-17

申请号：DE3778961

申请日：1987-02-23

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CONTIERO CLAUDIO ,  ANDREINI ANTONIO ,  GALBIATI PAOLA

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/336 ,  H01L29/10

Abstract: Described is an improved fabrication process for vertical DMOS cells contemplating the prior definition of the gate areas by placing a polycrystalline silicon gate electrode and utilizing the gate electrode itself as a mask for implanting and diffusing the body regions, while forming the short region is carried out using self-alignment techniques which permit an easy control of the lateral extention of the region itself. A noncritical mask defines the zone where the short circuiting contact between the source electrode and the source and body regions in the middle of the DMOS cell will be made, allowing also to form the source region. Opening of the relative contact is also effected by self alignment technique, further simplifying the process.

公开(公告)号：IT1227104B

公开(公告)日：1991-03-15

申请号：IT2208588

申请日：1988-09-27

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CONTIERO CLAUDIO ,  MURARI BRUNO

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/58 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H02H11/00 ,  H01L

Abstract: An integrated circuit (1) self-protected agianst reversal of the supply battery (2) polarity comprises a first DMOS power transistor (T1) connected with its source electrode (S1) side to an electric load (R1) to be driven toward ground, and a second, protective DMOS transistor (T2) which is connected with its source electrode (S2) side to a positive pole (Vc) of the battery (2) and with its drain electrode (D2) side to the drain electrode (D1) of the first transistor (T1). The first T1) and second (T2) transistors have in common the drain region formed on a single pod (9) in the semiconductor substrate (4).