公开(公告)号：ITMI920339D0

公开(公告)日：1992-02-17

申请号：ITMI920339

申请日：1992-02-17

Applicant: ST MICROELECTRONICS SRL ,  SGS THOMSON MICROELECTRONICS

Inventor： ANDREINI ANTONIO ,  CONSIGLIO PIETRO ,  ERRATICO PIETRO ,  RAVANELLI ENRICO MARIA ALFONSO

IPC: H04M1/00 ,  H04M1/31 ,  H04M1/74 ,  H04M1/82 ,  H01R3/00 ,  H04M

公开(公告)号：ITMI920339A1

公开(公告)日：1993-08-18

申请号：ITMI920339

申请日：1992-02-17

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： ANDREINI ANTONIO ,  CONSIGLIO PIETRO ,  ERRATICO PIETRO ,  RAVANELLI ENRICO MARIA ALFONSO

IPC: H04M1/00 ,  H04M20060101 ,  H04M1/31 ,  H04M1/74 ,  H04M1/82

公开(公告)号：DE3788438T2

公开(公告)日：1994-04-07

申请号：DE3788438

申请日：1987-01-21

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CONTIERO CLAUDIO ,  GALBIATI PAOLA ,  ANDREINI ANTONIO

IPC: H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/78 ,  H01L21/82

Abstract: This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant (25) on the surface of an epitaxial layer (2), without masking, and arsenic implant (28) in predetermined locations of the epitaxial layer surface by means of an appropriate mask (27). A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms (72,35-37), but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N⁺ type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted

公开(公告)号：DE3788438D1

公开(公告)日：1994-01-27

申请号：DE3788438

申请日：1987-01-21

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CONTIERO CLAUDIO ,  GALBIATI PAOLA ,  ANDREINI ANTONIO

IPC: H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/78 ,  H01L21/82

Abstract: This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant (25) on the surface of an epitaxial layer (2), without masking, and arsenic implant (28) in predetermined locations of the epitaxial layer surface by means of an appropriate mask (27). A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms (72,35-37), but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N⁺ type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted

公开(公告)号：DE3751313T2

公开(公告)日：1996-02-01

申请号：DE3751313

申请日：1987-03-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： ANDREINI ANTONIO ,  CONTIERO CLAUDIO ,  GALBIATI PAOLA

IPC: H01L21/033 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L21/82

公开(公告)号：DE3751313D1

公开(公告)日：1995-06-29

申请号：DE3751313

申请日：1987-03-24

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： ANDREINI ANTONIO ,  CONTIERO CLAUDIO ,  GALBIATI PAOLA

IPC: H01L21/033 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L21/82

公开(公告)号：DE3778961D1

公开(公告)日：1992-06-17

申请号：DE3778961

申请日：1987-02-23

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CONTIERO CLAUDIO ,  ANDREINI ANTONIO ,  GALBIATI PAOLA

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/336 ,  H01L29/10

Abstract: Described is an improved fabrication process for vertical DMOS cells contemplating the prior definition of the gate areas by placing a polycrystalline silicon gate electrode and utilizing the gate electrode itself as a mask for implanting and diffusing the body regions, while forming the short region is carried out using self-alignment techniques which permit an easy control of the lateral extention of the region itself. A noncritical mask defines the zone where the short circuiting contact between the source electrode and the source and body regions in the middle of the DMOS cell will be made, allowing also to form the source region. Opening of the relative contact is also effected by self alignment technique, further simplifying the process.