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    MANUFACTURE OF SEMICONDUCTOR DEVICE HAVING VARIOUS BURIED REGIONS
    1.
    发明专利
    MANUFACTURE OF SEMICONDUCTOR DEVICE HAVING VARIOUS BURIED REGIONS 失效

    公开(公告)号：JPH1055976A

    公开(公告)日：1998-02-24

    申请号：JP7904197

    申请日：1997-03-12

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PALMIERI MICHELE ,  GALBIATI PAOLA ,  VECCHI LODOVICA

    IPC: H01L21/265 ,  H01L21/266 ,  H01L21/74 ,  H01L21/8249

    Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing an integrated device, which has additional buried layers while masks fewer than the number of masks used in a conventional method are used. SOLUTION: This is a method of doping a P-type supporting material 50 by a method wherein silicon nitride masks 52 are formed, N-type impurities are implanted in the supporting material 50 using these masks, resist masks 54 to be remained with at least one region, which is exposed and contains one part of a nitride, of the material 50 are formed on the material 50, the material 50 is performed a high-temperature treatment under an oxidative environment, silicon dioxide pads are formed on regions, which are not covered with the masks 52, of the material 50 and a P-type impurity implantation is performed in the regions sectioned into the boundaries defined by the pads. Then, the removal of the pads, the formation of epitaxial layers in a conventional method and a selective doping for forming P-type and N-type regions in the epitaxial layers are continuously performed in the method.

    3.
    发明专利
    未知

    公开(公告)号：IT8424126D0

    公开(公告)日：1984-12-18

    申请号：IT2412684

    申请日：1984-12-18

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： CONTIERO CLAUDIO ,  GALBIATI PAOLA

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L29/78 ,  C07C

    Abstract: The disclosed bridge circuit is fabricated using power MOS technology. Common terminals of the bridge circuit are integrated into common regions in the implementation. Electrodes, typically coupled together in the bridge circuit, are implemented by a shared conducting region in the integrated circuit of the semiconductor chip. By integrating the elements of the circuit, less area of the semiconductor chip is required as compared to an implementation involving 4 (four) discrete elements. Diodes are fabricated across the transistors to protect the elements against reverse biasing.

    4.
    发明专利
    未知

    公开(公告)号：DE3788438T2

    公开(公告)日：1994-04-07

    申请号：DE3788438

    申请日：1987-01-21

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： CONTIERO CLAUDIO ,  GALBIATI PAOLA ,  ANDREINI ANTONIO

    IPC: H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/78 ,  H01L21/82

    Abstract: This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant (25) on the surface of an epitaxial layer (2), without masking, and arsenic implant (28) in predetermined locations of the epitaxial layer surface by means of an appropriate mask (27). A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms (72,35-37), but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N⁺ type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted

    5.
    发明专利
    未知

    公开(公告)号：DE3788438D1

    公开(公告)日：1994-01-27

    申请号：DE3788438

    申请日：1987-01-21

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： CONTIERO CLAUDIO ,  GALBIATI PAOLA ,  ANDREINI ANTONIO

    IPC: H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8236 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/78 ,  H01L21/82

    Abstract: This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant (25) on the surface of an epitaxial layer (2), without masking, and arsenic implant (28) in predetermined locations of the epitaxial layer surface by means of an appropriate mask (27). A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms (72,35-37), but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N⁺ type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted

    10.
    发明专利
    未知

    公开(公告)号：IT1305634B1

    公开(公告)日：2001-05-15

    申请号：ITVA980001

    申请日：1998-01-19

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： ROSSI DOMENICO ,  GALBIATI PAOLA ,  BERTOLINI LUCA ,  POZZONI MASSIMO ,  PEDRAZZINI GIORGIO ,  CORDINI PAOLO ,  PALMIERI MICHELE

    IPC: H01L27/02

    Abstract: In a junction isolated integrated circuit including power DMOS transistors formed in respective well regions or in an isolated epitaxial region on a substrate of opposite type of conductivity, circuits are formed in a distinct isolated region sensitive to oversupply and/or belowground effects. These effects are caused by respective power DMOS transistors coupled to the supply rail or ground. These effects are alternatively controllable by specifically shaped layout arrangements, and may be effectively protected from both effects. This is achieved by interposing between the region of sensitive circuits and the region containing the power DMOS transistors for which the alternatively implementable circuital arrangements are not formed, the region containing the power DMOS transistors coupled to the supply rail or to a ground rail for which the alternatively implementable arrangements are formed. The special interposition separates and shields the sensitive circuits from the power device whose oversupply or belowground effect is not countered by specific circuit arrangements.

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