公开(公告)号：EP1091408A1

公开(公告)日：2001-04-11

申请号：EP99830628.6

申请日：1999-10-07

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo ,  Maurelli, Alfonso ,  Zatelli, Nicola

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

Abstract: The memory cell (101) is of the type with a single level of polysilicon, and comprises a sensing transistor (20) and a select transistor (21). The sensing transistor (20) comprises a control gate region (6) with a second type of conductivity, formed in a first region of active area (30) of a substrate (3) of semiconductor material, and a floating gate region (9) which extends transversely relative to the first region of active area (30). The control gate region (6) of the sensing transistor (20) is surrounded by a first well (103) with the first type of conductivity, and in turn is surrounded, below and laterally, by a second well (104) with the second type of conductivity, thus forming a triple well structure (142). A second triple well structure (140) can be formed in a second region of active area (31) adjacent to the first region of active area (30), and can accommodate conduction regions (4, 5, 12, 14, 15) of the sensing transistor and of the select transistor (21).

Abstract translation: 存储单元（101）是具有单层多晶硅的类型，并且包括感测晶体管（20）和选择晶体管（21）。 感测晶体管（20）包括形成在半导体材料的衬底（3）的有源区域（30）的第一区域中的具有第二类型导电性的控制栅极区域（6）和浮动栅极区域（9） 其相对于有源区域（30）的第一区域横向延伸。 感测晶体管（20）的控制栅极区域（6）由具有第一类型导电性的第一阱（103）围绕，并且又由第二阱（104）包围，在第二阱（104）的下面和侧面，第二阱 导电类型，从而形成三重阱结构（142）。 可以在与有源区域（30）的第一区域相邻的有源区域（31）的第二区域中形成第二三阱结构（140），并且可以适应传导区域（4,5,12,14,15） 感测晶体管和选择晶体管（21）。

公开(公告)号：EP1011137A1

公开(公告)日：2000-06-21

申请号：EP98830757.5

申请日：1998-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： Colombo, Paolo ,  Maurelli, Alfonso

IPC: H01L21/8239 ,  H01L27/02

CPC classification number: H01L27/11521 ,  H01L27/0266 ,  H01L29/66659

Abstract: A method of forming a doped region (8,9) in an integrated circuit which includes a matrix of memory cells and Lightly Doped Drain (LDD) transistors and which is fabricated by means of a process providing for a Self-Aligned Source (SAS) masked etch and implant and for a selective salicidation of some doped regions, the doped region suitable for forming an integrated resistor and/or an abrupt-profile source/drain region of a transistor. The doped region (8,9) is formed by introducing into a semiconductor layer (2) of a first conductivity type a dopant of a second conductivity type, exploiting the SAS masked implant used to form source regions (5) of the matrix of memory cells. At least a portion of a surface of the doped region (8,9) is prevented from being salicidated by using as a protective mask a portion of a dielectric layer (15) from which insulating sidewall spacers (17) for the LDD transistors are formed.

Abstract translation: 在集成电路中形成掺杂区域（8,9）的方法，其包括存储器单元的一个矩阵和轻掺杂漏极（LDD）晶体管，并且借助于该制造提供一自对准源极（SAS）的处理 掩蔽蚀刻和植入物和用于一些掺杂区域的选择性硅化，适于晶体管的集成电阻和/或突然轮廓源极/漏极区域的形成掺杂区域。 该掺杂区域（8,9）被引入到第一导电类型的第二导电类型的掺杂剂的半导体层（2），利用该SAS掩模注入用来形成源极区域（5）形成的存储器矩阵的 细胞。 至少所述掺杂区域（8,9）的表面的一部分从通过使用作为保护掩模从哪个绝缘侧壁间隔物（17），用于在LDD晶体管的电介质层（15）的一部分被salicidated被防止形成 ，

公开(公告)号：EP1001466A1

公开(公告)日：2000-05-17

申请号：EP98830675.9

申请日：1998-11-10

Applicant: STMicroelectronics S.r.l.

Inventor： Riva, Carlo ,  Ghezzi, Paolo ,  Maurelli, Alfonso

IPC: H01L27/105 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823462 ,  H01L27/105

Abstract: High-voltage transistor structure, particularly for handling programming and/or programming and erasing voltages for electrically programmable and/or electrically programmable and erasable non-volatile memory cells which are integrated together with the high-voltage transistor and a low-voltage logic circuitry in a same semiconductor chip, the logic circuitry comprising first conductivity type channel transistors and second conductivity type channel transistors respectively formed inside second conductivity type wells (2) and first conductivity type wells (3), the first and second conductivity type wells (2,3) formed in a common substrate (1) of the first conductivity type which forms a common substrate of the semiconductor chip, the high-voltage transistor comprising an insulated gate electrode (10) and source and drain electrodes (9) at the sides of the insulated gate electrode (10). The insulated gate electrode (10) is insulated from the underlying common substrate (1) of the first conductivity type by a portion of a thick field oxide (4), and the source and drain electrodes (9) are doped regions of a second conductivity type formed directly in said common substrate (1).

Abstract translation: 高压晶体管结构，特别是用于处理编程和/或编程和擦除电压为电可编程和/或电可编程和可擦除的非易失性存储器，其与所述高电压晶体管和低电压逻辑电路集成在一起的单元 相同的半导体芯片，所述逻辑电路包括第一导电类型沟道的晶体管及第二导电类型沟道的晶体管内第二导电型阱分别形成（2）和第一导电类型的井（3）中，第一及第二导电型的井（2.3 衬底），形成在一个共同的（1），其形成在半导体芯片的一个公共基底上的第一导电类型的，高电压晶体管绝缘栅电极（10）和源极的包括电极和漏电极（9）的侧面 绝缘栅电极（10）。 绝缘栅电极（10）被从底层共同基底绝缘（1）由一个厚的场氧化物的部分的第一导电类型的（4），以及源电极和漏电极（9）掺杂一第二导电性的区域 直接在型形成在所述共用基板（1）。

公开(公告)号：EP0993036A1

公开(公告)日：2000-04-12

申请号：EP98830595.9

申请日：1998-10-09

Applicant: STMicroelectronics S.r.l.

Inventor： Baldi, Livio ,  Maurelli, Alfonso

IPC: H01L21/8239 ,  H01L27/105 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11539 ,  H01L27/11546

Abstract: Method of manufacturing an integrated semiconductor device comprising at least one non-volatile floating gate memory cell (20) and at least one logic transistor (10). Said method comprises a first step of growing a first gate oxide layer (2) over a silicon substrate (1), a second step of depositing a first polysilicon layer (3) over the first gate oxide layer (2), a third step of selectively etching and removing the first polysilicon layer (3) in order to define the floating gate (31) of the memory cell (20), a fourth step of introducing dopant in order to obtain source (5) and drain (6) regions of the memory cell (20), a fifth step of depositing a dielectric layer (7), a sixth step of selectively etching and removing the dielectric layer (7) and the first polysilicon layer (3) in a region wherein the logic transistor (10) will be formed, a seventh step of depositing a second polysilicon layer (11), an eighth step of selectively etching and removing the second polysilicon layer (11) in order to define the gate (32) of the logic transistor (10) and the control gate (33) of the memory cell (20). Between the sixth step and the seventh step a first sub-step of removing the first gate oxide layer (2) in the region for the logic transistor (10), a second sub-step of growing a second oxide gate layer (9) over the region, the second gate oxide layer (9) being different from, eg. having a smaller thickness than that of the first gate oxide layer (2), are provided. A high voltage transistor (30) having a gate oxide constituted by said first gate oxide layer (2) and a gate electrode constituted by said first polysilicon layer (3) may furthermore be formed together with said memory cell (20) and said logic transistor (10).

Abstract translation: 制造集成半导体器件的方法，包括至少一个非易失性浮栅存储器单元（20）和至少一个逻辑晶体管（10）。 所述方法包括生长第一栅氧化物层的第一步骤（2）在硅衬底（1），沉积第一多晶硅层（3）在所述第一栅氧化物层（2），第三步骤的第二步骤 选择性地蚀刻并以限定存储器单元的浮置栅极（31）（20），以获得源将掺杂剂引入的第四工序除去第一多晶硅层（3）（5）和漏区（6）的区域 存储器单元（20），沉积电介质层（7），选择性地蚀刻的第六步骤以及去除所述电介质层（7）和所述第一多晶硅层的第五步骤（3）的区域中worin逻辑晶体管（10 ）将被形成的，沉积第二多晶硅层（11），（在选择性地蚀刻的第八步骤，并且为了限定逻辑（10的栅极（32）去除第二多晶硅层11）晶体管的第七步骤），并 存储器单元的控制栅极（33）（20）。 第六步骤和第七步骤，用于所述逻辑晶体管（10），生长第二氧化物栅极层的第二子步骤中除去在该区域所述第一栅氧化层（2）的第一子步骤（9）之间过 的区域中，所述第二栅极氧化物层（9）不同于，具有比被设置（2）例如，第一栅极氧化物层的厚度较小.. 具有由所述第一栅氧化层（2）构成的栅氧化层和由所述第一多晶硅层（3）构成的栅极电极的高电压晶体管（30）可以进一步被一起与所述存储单元（20）和所述逻辑晶体管构成 （10）。

公开(公告)号：EP0926687A1

公开(公告)日：1999-06-30

申请号：EP97830693.4

申请日：1997-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo ,  Maurelli, Alfonso ,  Olivo, Marco

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/106 ,  G11C29/52 ,  G11C29/76

Abstract: A method of self-test and correction of errors due to a loss charge for a flash memory constituted by an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided, implemented by realizing at least an additional row and at least an additional column of cells for each memory sector; storing parity codes is the additional row and column, and carrying out periodically a self-test routine and eventual correction routine composed of the following steps:

* repeating the sequential reading per bytes and parity check;
* verifying the consistency of the parity value with the value stored in the respective parity bit;
* if the verification is negative, retaining the current row address and proceeding to sequentially verify column parity starting from the first column until identifying the column for which the verification yields a negative result, and if the failed bit so individuated is "1" reprogramming it to "0".

Abstract translation: 由由阵列或矩阵的单元（位）构成的闪存的损耗电荷的自检和校正错误的方法，其由行和列组织，可由矩阵分割的整个扇区可擦除和编程， 通过为每个存储器扇区实现至少一个附加行和至少一个附加列的单元来实现; 存储奇偶校验码是附加行和列，并且周期性地执行自检程序和最终校正程序，其由以下步骤组成：重复每字节的顺序读取和奇偶校验; 验证奇偶校验值与存储在相应奇偶校验位中的值的一致性; 如果验证是否定的，保留当前的行地址并继续从第一列开始顺序验证列奇偶校验，直到识别验证产生否定结果的列，并且如果如此个性化的故障位为“1”，则重新编程为 “0”。