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    Page buffer for multi-level NAND programmable memories
    25.
    发明公开
    Page buffer for multi-level NAND programmable memories 有权
    Multipegel-NAND-Speicher的程序设计师Seitenspeicher

    公开(公告)号：EP1748445A1

    公开(公告)日：2007-01-31

    申请号：EP05106972.2

    申请日：2005-07-28

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Crippa, Luca ,  Missiroli, Chiara ,  Bovino, Angelo ,  Ravasio, Roberto ,  Micheloni, Rino

    IPC: G11C11/56

    CPC classification number: G11C11/5628

    Abstract: A page buffer (130) for an electrically programmable memory (100) is provided. The electrically programmable memory includes a plurality of memory cells (110) arranged in a plurality of bit lines (BLe,BLo) of memory cells and forming a plurality of individually-selectable memory sets. The electrically programmable memory includes a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell. The data bits include at least a first data bits group (MSB) and a second data bits group (LSB), the first data bits groups and, respectively, the second data bits groups stored in the memory cells of one of said individually-selectable memory cell sets forming at least a first memory page and a second memory page, respectively. The first and second memory pages are individually addressable in reading and writing. The page buffer comprises at least one read/program unit (205) having a coupling line (SO) operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cells sets. The read/program unit comprises enabling means (230-1, 230-2, 252, 254, 256, 258, 272, 274, 276, 278) for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits (MSB) of the selected memory cell, and an existing data value already stored in the second group of data bits (LSB) of the selected memory cell. The enabling means comprise reading means (256, 258, 260, 230-2) for retrieving the existing data value; means (252, 254, 230-1) for receiving an indication of the target data value; combining means (272, 274, 276, 278) for combining the received target data value with the retrieved existing data value, thereby modifying said indication of the target data value so as to obtain a modified indication; and conditioning means (272, 274) included in the combining means for conditioning a potential of the coupling line based on the existing data value and the modified indication, so as to cause the coupling line to take the program enabling potential or the program inhibition potential.

    Abstract translation: 提供了一种用于电可编程存储器（100）的页缓冲器（130）。 电可编程存储器包括布置在存储器单元的多个位线（BLe，BLo）中的多个存储单元（110），并形成多个单独选择的存储器组。 电可编程存储器包括针对每个存储器单元定义的多个不同的编程状态，对应于每个存储单元中可存储的数据位数N> = 2。 数据位包括至少第一数据位组（MSB）和第二数据位组（LSB），第一数据位组和分别存储在所述可单独选择的一个存储单元中的第二数据位组 存储单元组分别形成至少第一存储器页面和第二存储器页面。 第一和第二个存储器页面在读取和写入时可单独寻址。 页面缓冲器包括至少一个具有可操作地与至少一个所述位线相关联的耦合线（SO）的读/写单元（205），并且适于至少临时存储从或写入 存储在所选存储单元组的存储单元中的第一或第二存储器页。 读/程序单元包括启用装置（230-1,230-2,252,254,256,258,272,274,276,278,278,276,278,272,276,278,276,278,278,276,278,276,278,278,276,278,278,276,278,278,276,278,278,276,278,278,278,276,278,278,278,276,278,278,2 行程序中的一个，使程序启用电位和程序禁止电位，调节为要存储在所选择的存储器单元的第一组数据位（MSB）中的目标数据值，以及已经存储在第二个存储单元中的现有数据值 所选存储单元的数据位组（LSB）组。 启用装置包括用于检索现有数据值的读取装置（256,258,260,230-2）; 用于接收目标数据值的指示的装置（252,254,230-1）; 用于将接收到的目标数据值与所检索的现有数据值组合的组合装置（272,274,276,278），从而修改目标数据值的所述指示以获得修改的指示; 以及包括在组合装置中的调节装置（272,274），用于基于现有数据值和修改的指示调节耦合线的电位，以使耦合线采取程序使能电位或编程抑制电位 。

    Method for accessing a multilevel nonvolatile memory device of the flash NAND type
    26.
    发明公开
    Method for accessing a multilevel nonvolatile memory device of the flash NAND type 有权
    Verfahren zum Zugreifen auf einenichtflüchtigeMehrpegelspeichervorrichtung vom Typ FLASH NAND

    公开(公告)号：EP1746604A1

    公开(公告)日：2007-01-24

    申请号：EP05106783.3

    申请日：2005-07-22

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Bovino, Angelo ,  Altieri, Vincenzo ,  Ravasio, Roberto ,  Micheloni, Rino ,  De Matteis, Mario

    IPC: G11C11/56

    CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C2211/5641

    Abstract: Multi-level programming (30-42) allows for writing a first and a second bit in selected cells (3) by separately programming (30-32) a first bit (LSB) from a second bit (MSB). Programming (30-32) of the first bit determines a shifting (32) from a first threshold level (A) to a second threshold level (B); programming (36-42) of the second bit requires a preliminary reading (36-40) to detect whether the first bit (LSB) has been modified; performing a first writing step (42) to bring the cell to a third threshold voltage (C) if the first bit has been modified and performing a second writing step (42) to bring the selected cell to a fourth threshold voltage (D) different from the third threshold level if the first bit has not been modified. The memory array (2) divided into a first portion (2a) where data are stored using multiple threshold levels corresponding to a plurality of bits, and a second portion (2b) where data are stored using two threshold levels corresponding to a single bit. For increasing reading and program reliability, during preliminary reading (40) of the second portion (2b) a reading result is forced to correspond to the first threshold level.

    Abstract translation: 多级编程（30-42）允许通过从第二位（MSB）单独编程（30-32）第一位（LSB）来在所选单元（3）中写入第一位和第二位。 第一位的编程（30-32）确定从第一阈值电平（A）到第二阈值电平（B）的移位（32）; 第二位的编程（36-42）需要初步读取（36-40）来检测第一位（LSB）是否已被修改; 执行第一写入步骤（42），如果第一位已被修改并使单元进入第三阈值电压（C），并执行第二写入步骤（42）以使所选择的单元达到不同的第四阈值电压（D） 如果第一位未被修改，则从第三阈值水平。 存储器阵列（2）被划分为第一部分（2a），其中使用与多个位相对应的多个阈值级别存储数据;以及第二部分（2b），其中使用与单个位对应的两个阈值电平存储数据。 为了增加读取和编程可靠性，在第二部分（2b）的初步读取（40）期间，读取结果被迫对应于第一阈值水平。

    NAND flash memory device with compacted cell threshold voltage distribution
    27.
    发明公开
    NAND flash memory device with compacted cell threshold voltage distribution 审中-公开
    NAND Flash Speicher mit komprimierter Verteilung der Schwellspannungen der Speicherzellen

    公开(公告)号：EP1729306A1

    公开(公告)日：2006-12-06

    申请号：EP05104742.1

    申请日：2005-06-01

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Ravasio, Roberto ,  Motta, Ilaria

    IPC: G11C16/34

    CPC classification number: G11C16/3404 ,  G11C16/3409

    Abstract: A flash memory device with NAND architecture (100) is proposed. The memory device includes a matrix of memory cells (110) each one having a programmable threshold voltage, wherein the matrix includes at least one sector individually erasable (115) and it is arranged in a plurality of rows and columns with the cells of each row connected to the corresponding word line (WL) and the cells of each column arranged in a plurality of strings (125) of cells connected in series, the strings of each column being connected to a corresponding bit line (BL), wherein the memory device further includes means (320) for erasing the cells of a selected sector, and means (330) for restoring the threshold voltage of the erased cells, wherein the means for restoring acts in succession on each of a plurality of blocks of the sector, for each one of a set of selected bit lines the block including a group of cells connected to a set of selected word lines, the means for restoring including means (446a, 446b) for reading each group with respect to a limit value exceeding a reading reference value, means (451a, 451b) for programming only each group wherein the threshold voltage of at least one group does not reach said limit value, and means (449a, 449b) for stopping the restoring in response to the reaching of the limit value by at least one sub-set of the groups.

    Abstract translation: 提出了具有NAND架构（100）的闪存器件。 存储器件包括每个具有可编程阈值电压的存储器单元（110）的矩阵，其中该矩阵包括至少一个可单独地擦除的扇区（115），并且它被布置成多个行和列，每行的单元格 连接到相应的字线（WL）和排列成串联连接的多个单元串（125）的每列的单元，每列的串连接到对应的位线（BL），其中存储器件 还包括用于擦除所选扇区的单元的装置（320），以及用于恢复已擦除单元的阈值电压的装置（330），其中用于恢复的装置依次在该扇区的多个块中的每个块上作用， 一组选定位线中的每一个，包括连接到一组所选字线的一组单元的单元，所述恢复装置包括用于相对于超过一个限制值的每个组读取每个组的装置（446a，446b） 读取参考值，用于仅编程至少一个组的阈值电压未达到所述极限值的每个组的装置（451a，451b）以及用于响应于达到极限而停止恢复的装置（449a，449b） 至少一个组的子集的值。

    Charge-pump type voltage-boosting device with reduced ripple, in particular for non-volatile flash memories
    28.
    发明公开
    Charge-pump type voltage-boosting device with reduced ripple, in particular for non-volatile flash memories 审中-公开
    电荷泵型电压失真减小尤其是对于非易失性快闪存储器的电压提升电路

    公开(公告)号：EP1727146A1

    公开(公告)日：2006-11-29

    申请号：EP05425348.9

    申请日：2005-05-20

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Ragone, Giancarlo ,  Sangalli, Miriam ,  Crippa, Luca ,  Micheloni, Rino

    IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07

    CPC classification number: G11C5/145 ,  G11C16/30 ,  H02M3/073 ,  H02M2001/007

    Abstract: Voltage-boosting device having a supply input (9) receiving a supply voltage (Vdd), and a high-voltage output (3). The device (1) is formed by a plurality of charge-pump stages (14) series-connected between the supply input (9) and the high-voltage output (3). Each charge-pump stage (14) has a respective enabling input receiving an enabling signal (EN1, ..., ENn-1, ENn). A control circuit (4, 8) formed by a plurality of comparators (8.1, ..., 8.n-1, 8.n) is connected to the high-voltage output (3) and generates the enabling signals on the basis of the comparison between the voltage on the high-voltage output (3) and a plurality of reference voltages (REF1, ..., ..., REFn-1, REFn), one for each comparator. The charge-pump stages (14) are grouped into sets of stages (13.1, ..., 13.n-1, 13.n), and the stages belonging to a same set receive a same enabling signal (EN1, ENn-1, ENn); thus, as many comparators as there are sets of stages are present.

    Abstract translation: 升压具有供电输入端（9），接收电源电压（Vdd）的装置，和一个高电压输出端（3）。 所述装置（1）通过的电荷泵级（14）串联连接在电源输入端（9）和所述输出高电压（3）之间形成的多个。 每个电荷泵级（14）具有一个respectivement使能输入处接收使能信号（EN1，...，ENN-1，ENN）。 控制电路（4,8）由比较器形成的多个（8.1，...，8.n.-1，8.n.）连接到高电压输出端（3）和基因率使能信号的基础上 在高电压输出端（3）的基准电压的多个电压之间的比较和（REF1，...，...，REF N-1，REF n）时，一个用于每个比较器。 电荷泵级（14）被分成组级（13.1，...，13.n-1，13.n），并且属于同一组的各个阶段接收相同的使能信号（EN1，ENn- 1，ENN）; 因此，许多比较，因为有套阶段都存在。

    Low-ripple boosted voltage generator
    29.
    发明公开
    Low-ripple boosted voltage generator 审中-公开
    Spannungserhöherschaltungmit geringer Ausgangswelligkeit

    公开(公告)号：EP1677308A1

    公开(公告)日：2006-07-05

    申请号：EP05425001.4

    申请日：2005-01-03

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Ragone, Giancarlo ,  Sangalli, Miriam ,  Micheloni, Rino

    IPC: G11C5/14

    CPC classification number: G11C5/145

    Abstract: The output voltage ripple of a single stage or a multi-stage charge pump is significantly reduced by introducing in the voltage generator a cascode connected output transistor. In operation, this output transistor is always in a conduction state and is controlled with a voltage having a smaller ripple than the voltage output by the charge pump.

    Abstract translation: 通过在电压发生器中引入共源共栅输出晶体管，可以显着降低单级或多级电荷泵的输出电压纹波。 在工作中，该输出晶体管总是处于导通状态，并且具有比电荷泵输出的电压小的纹波的电压来控制。

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