Abstract:
A page buffer (130) for an electrically programmable memory (100) is provided. The electrically programmable memory includes a plurality of memory cells (110) arranged in a plurality of bit lines (BLe,BLo) of memory cells and forming a plurality of individually-selectable memory sets. The electrically programmable memory includes a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell. The data bits include at least a first data bits group (MSB) and a second data bits group (LSB), the first data bits groups and, respectively, the second data bits groups stored in the memory cells of one of said individually-selectable memory cell sets forming at least a first memory page and a second memory page, respectively. The first and second memory pages are individually addressable in reading and writing. The page buffer comprises at least one read/program unit (205) having a coupling line (SO) operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cells sets. The read/program unit comprises enabling means (230-1, 230-2, 252, 254, 256, 258, 272, 274, 276, 278) for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits (MSB) of the selected memory cell, and an existing data value already stored in the second group of data bits (LSB) of the selected memory cell. The enabling means comprise reading means (256, 258, 260, 230-2) for retrieving the existing data value; means (252, 254, 230-1) for receiving an indication of the target data value; combining means (272, 274, 276, 278) for combining the received target data value with the retrieved existing data value, thereby modifying said indication of the target data value so as to obtain a modified indication; and conditioning means (272, 274) included in the combining means for conditioning a potential of the coupling line based on the existing data value and the modified indication, so as to cause the coupling line to take the program enabling potential or the program inhibition potential.
Abstract:
Multi-level programming (30-42) allows for writing a first and a second bit in selected cells (3) by separately programming (30-32) a first bit (LSB) from a second bit (MSB). Programming (30-32) of the first bit determines a shifting (32) from a first threshold level (A) to a second threshold level (B); programming (36-42) of the second bit requires a preliminary reading (36-40) to detect whether the first bit (LSB) has been modified; performing a first writing step (42) to bring the cell to a third threshold voltage (C) if the first bit has been modified and performing a second writing step (42) to bring the selected cell to a fourth threshold voltage (D) different from the third threshold level if the first bit has not been modified. The memory array (2) divided into a first portion (2a) where data are stored using multiple threshold levels corresponding to a plurality of bits, and a second portion (2b) where data are stored using two threshold levels corresponding to a single bit. For increasing reading and program reliability, during preliminary reading (40) of the second portion (2b) a reading result is forced to correspond to the first threshold level.
Abstract:
A flash memory device with NAND architecture (100) is proposed. The memory device includes a matrix of memory cells (110) each one having a programmable threshold voltage, wherein the matrix includes at least one sector individually erasable (115) and it is arranged in a plurality of rows and columns with the cells of each row connected to the corresponding word line (WL) and the cells of each column arranged in a plurality of strings (125) of cells connected in series, the strings of each column being connected to a corresponding bit line (BL), wherein the memory device further includes means (320) for erasing the cells of a selected sector, and means (330) for restoring the threshold voltage of the erased cells, wherein the means for restoring acts in succession on each of a plurality of blocks of the sector, for each one of a set of selected bit lines the block including a group of cells connected to a set of selected word lines, the means for restoring including means (446a, 446b) for reading each group with respect to a limit value exceeding a reading reference value, means (451a, 451b) for programming only each group wherein the threshold voltage of at least one group does not reach said limit value, and means (449a, 449b) for stopping the restoring in response to the reaching of the limit value by at least one sub-set of the groups.
Abstract:
Voltage-boosting device having a supply input (9) receiving a supply voltage (Vdd), and a high-voltage output (3). The device (1) is formed by a plurality of charge-pump stages (14) series-connected between the supply input (9) and the high-voltage output (3). Each charge-pump stage (14) has a respective enabling input receiving an enabling signal (EN1, ..., ENn-1, ENn). A control circuit (4, 8) formed by a plurality of comparators (8.1, ..., 8.n-1, 8.n) is connected to the high-voltage output (3) and generates the enabling signals on the basis of the comparison between the voltage on the high-voltage output (3) and a plurality of reference voltages (REF1, ..., ..., REFn-1, REFn), one for each comparator. The charge-pump stages (14) are grouped into sets of stages (13.1, ..., 13.n-1, 13.n), and the stages belonging to a same set receive a same enabling signal (EN1, ENn-1, ENn); thus, as many comparators as there are sets of stages are present.
Abstract:
The output voltage ripple of a single stage or a multi-stage charge pump is significantly reduced by introducing in the voltage generator a cascode connected output transistor. In operation, this output transistor is always in a conduction state and is controlled with a voltage having a smaller ripple than the voltage output by the charge pump.