公开(公告)号：WO2007027907A3

公开(公告)日：2009-05-07

申请号：PCT/US2006034051

申请日：2006-09-01

Applicant: UNIV COLUMBIA ,  VON GUTFELD ROBERT J ,  WEST ALAN C

Inventor： VON GUTFELD ROBERT J ,  WEST ALAN C

IPC: C23F1/00 ,  C25F3/02 ,  C25F7/00

CPC classification number: C25F3/02 ,  B81C1/00571 ,  B81C2201/0133 ,  B81C2201/0139 ,  B81C2201/0142 ,  C23F1/02 ,  C23F1/08 ,  H05K3/068 ,  H05K2203/1105 ,  H05K2203/1115

Abstract: Systems and methods for etching topographic features in non- crystalline or metallic substrates are provided. A protective material is placed and patterned on a surface of the substrate to define exposed and protected regions of the substrate for etching in a liquid etchant having etching rates that are thermally activated. A nonuniform temperature profile is imposed on the substrate so that the temperatures and hence the etching rates at surfaces in the exposed regions are higher than those in the protected regions. Arrangements for imposing the nonuniform temperature profile include heating designated portions of the substrate with light radiation. Alternatively, the non-uniform temperature profile is developed as etching progresses by passing current pulses through the substrate in a manner that causes geometrically non-uniform heating of the substrate.

Abstract translation: 提供用于蚀刻非晶体或金属基底中的地形特征的系统和方法。 保护材料被放置并图案化在衬底的表面上以限定衬底的暴露和保护区域，以在具有热激活蚀刻速率的液体蚀刻剂中蚀刻。 对基板施加不均匀的温度曲线，使得暴露区域中的表面的温度和蚀刻速率高于受保护区域中的温度。 施加不均匀温度分布的布置包括用光辐射加热衬底的指定部分。 或者，当通过使电流脉冲以导致衬底的几何不均匀加热的方式通过衬底时蚀刻进行蚀刻而开发不均匀的温度分布。

公开(公告)号：WO2007027907A2

公开(公告)日：2007-03-08

申请号：PCT/US2006/034051

申请日：2006-09-01

Applicant: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK ,  VON GUTFELD, Robert, J. ,  WEST, Alan, C.

Inventor： VON GUTFELD, Robert, J. ,  WEST, Alan, C.

IPC: B05D5/04

CPC classification number: C25F3/02 ,  B81C1/00571 ,  B81C2201/0133 ,  B81C2201/0139 ,  B81C2201/0142 ,  C23F1/02 ,  C23F1/08 ,  H05K3/068 ,  H05K2203/1105 ,  H05K2203/1115

Abstract: Systems and methods for etching topographic features in non- crystalline or metallic substrates are provided. A protective material is placed and patterned on a surface of the substrate to define exposed and protected regions of the substrate for etching in a liquid etchant having etching rates that are thermally activated. A nonuniform temperature profile is imposed on the substrate so that the temperatures and hence the etching rates at surfaces in the exposed regions are higher than those in the protected regions. Arrangements for imposing the nonuniform temperature profile include heating designated portions of the substrate with light radiation. Alternatively, the non-uniform temperature profile is developed as etching progresses by passing current pulses through the substrate in a manner that causes geometrically non-uniform heating of the substrate.

Abstract translation: 提供用于蚀刻非晶体或金属基底中的地形特征的系统和方法。 保护材料被放置并图案化在衬底的表面上以限定衬底的暴露和保护区域，以在具有热激活蚀刻速率的液体蚀刻剂中蚀刻。 对基板施加不均匀的温度曲线，使得暴露区域中的表面的温度和蚀刻速率高于受保护区域中的温度。 施加不均匀温度分布的布置包括用光辐射加热衬底的指定部分。 或者，当通过使电流脉冲以导致衬底的几何不均匀加热的方式通过衬底时蚀刻进行蚀刻而开发不均匀的温度分布。

公开(公告)号：WO2004017361A2

公开(公告)日：2004-02-26

申请号：PCT/EP2003/009052

申请日：2003-08-14

Applicant: PERKINELMER OPTOELECTRONICS GMBH & CO. KG ,  HAUSNER, Martin

Inventor： HAUSNER, Martin

IPC: H01L

CPC classification number: H01L21/3065 ,  B81C1/00626 ,  B81C2201/0132 ,  B81C2201/0142 ,  H01L21/30655 ,  H01L21/3081

Abstract: Ein Verfahren zum selektiven Abtragen von Material aus der Oberfläche eines Substrats zur Bildung einer Vertiefung hat die Schritte Aufbringen einer Maske auf der Oberfläche des Substrats nach Massgabe des gewünschten selektiven Abtrags, und Trockenätzen des Substrats, wobei ein Metall, vorzugsweise Aluminium als Maskenmaterial verwendet wird. Es kann induktiv Energie in ein Plasma eingekoppelt werden.

Abstract translation: 从基底表面选择性地去除材料以形成凹陷的方法具有以下步骤：根据期望的选择性去除将掩模施加到基底的表面，并干燥 衬底，其中金属，优选铝被用作掩模材料。 它可以将能量感应耦合到等离子体中。

公开(公告)号：WO00067306A1

公开(公告)日：2000-11-09

申请号：PCT/DE2000/001296

申请日：2000-04-26

IPC: H05H1/46 ,  B01J19/08 ,  B81C1/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/66

CPC classification number: B81C1/00626 ,  B81C99/0065 ,  B81C2201/0132 ,  B81C2201/0142 ,  H01L21/3065 ,  H01L21/30655

Abstract: The invention relates to a method for the anisotropic etching of structures on a semiconductor body, in particular for etching recesses in a silicon body (18) which are defined laterally in a precise manner by an etching mask, using a plasma (28). An ion-accelerator voltage is applied to the semiconductor, at least during an etching step which continues for a predetermined period. Said ion-accelerator voltage is induced, in particular, by a high-frequency alternating current. The duration of the etching step is subdivided further into at least two etching periods, between which the applied ion-accelerator voltage is modified. A preferred embodiment contains two etching periods, whereby a higher accelerator voltage is used during the first etching period than during the second etching period. The duration of the first etching period can also be determined dynamically or statically during the etching steps using a device for detecting a polymer breakthrough. In addition, high frequency pulses or pulse packets with an adjustable pulse-pause ratio are preferably used to generate and adjust the level of the accelerator voltage.

Abstract translation: 一种用于在半导体本体结构的各向异性蚀刻方法，特别是提出了精确地通过等离子体（28）的方法用在硅体（18）蚀刻掩模的凹部横向限定。 在这种情况下，离子加速电压至少在一个正在进行的随着时间的蚀刻步骤，其特别是通过高频AC电压感应的预定时间段施加到半导体本体。 蚀刻步骤的持续时间进一步被划分成至少两个Ätzabschnitte之间所施加的离子加速电压在每种情况下改变。 优选两个Ätzabschnitte其中所述第一蚀刻部分更高的加速电压被用作在第二蚀刻步骤期间提供。 第一蚀刻部分的长度可以在由用于检测聚合物击穿的装置来蚀刻步骤来动态地或静态地确定。 优选的高频脉冲或脉冲分组用于具有可调节的脉冲间隔比用于产生和调节加速电压的电平。

公开(公告)号：WO2009126352A3

公开(公告)日：2009-12-23

申请号：PCT/US2009031516

申请日：2009-01-21

Applicant: SANDIA NAT LAB ,  PERROUD THOMAS D ,  PATEL KAMLESH D ,  MEAGHER ROBERT J

Inventor： PERROUD THOMAS D ,  PATEL KAMLESH D ,  MEAGHER ROBERT J

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/70

CPC classification number: G01N33/5005 ,  B01F3/0807 ,  B01F5/0471 ,  B01F13/0059 ,  B01L3/502707 ,  B01L3/502753 ,  B01L3/502761 ,  B01L3/502776 ,  B01L3/502784 ,  B01L2200/0668 ,  B01L2300/0816 ,  B01L2300/0864 ,  B01L2400/0688 ,  B81B2201/058 ,  B81C1/00047 ,  B81C1/00087 ,  B81C1/00119 ,  B81C1/00404 ,  B81C2201/0133 ,  B81C2201/0142 ,  Y10T137/9464 ,  Y10T428/24479

Abstract: Disclosed herein are methods of making micropores of a desired height and/or width between two isotropic wet etched features in a substrate which comprises single-level isotropic wet etching the two features using an etchant and a mask distance that is less than 2X a set etch depth. Also disclosed herein are methods using the micropores and microfluidic devices comprising the micropores.

Abstract translation: 本文公开了制造基底中的两个各向同性湿蚀刻特征之间的期望高度和/或宽度的微孔的方法，其包括使用蚀刻剂和掩模距离的单级各向同性湿法蚀刻两个特征，掩模距离小于集蚀刻的2X 深度。 本文还公开了使用包含微孔的微孔和微流体装置的方法。

公开(公告)号：WO2004037713A1

公开(公告)日：2004-05-06

申请号：PCT/IB2003/004586

申请日：2003-10-17

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  VAN BEEK, Jozef, T., M. ,  VAN GROOTEL, Margot

Inventor： VAN BEEK, Jozef, T., M. ,  VAN GROOTEL, Margot

IPC: B81C1/00

CPC classification number: B81C1/00595 ,  B81B2203/0323 ,  B81C2201/0142

Abstract: The invention relates to a method of manufacturing a micro-electromechanical device (10), in which are consecutively deposited on a substrate (1) a first electroconductive layer (2) in which an electrode (2A) is formed, a first electroinsulating layer (3) of a first material, a second electroinsulating layer (4) of a second material different from the first material, and a second electroconductive layer (5) in which a second electrode (5A) lying opposite the first electrode is formed which together with the first electrode (2A) and the first insulating layer (3) forms the device (10), in which after the second conductive layer (5) has been deposited, the second insulating layer (4) is removed by means of an etching agent which is selective with respect to the material of the second conductive layer (5). According to the invention for the first material and the second material materials are selected which are only limitedly selectively etchable with respect to each other and before depositing the second insulating layer (4) a further layer (6) is provided on top of the first insulating layer (3) of a further material that is selectively etchable with respect to the first material. In this way a silicon oxide and a silicon nitride may be applied for the insulating layers (3, 4) and thus the method according to the invention is very compatible with current IC processes. The second insulating layer (4) is preferably removed locally by etching, then the further layer (6) is completely removed by etching and, finally, the second insulating layer (4) is completely removed by etching.

Abstract translation: 本发明涉及一种制造微机电装置（10）的方法，其中连续地沉积在基板（1）上，形成有电极（2A）的第一导电层（2），第一电绝缘层 第一材料的第一电极和第二电极的第二电绝缘层（4）和与第一电极相对的第二电极（5A）的第二导电层（5） 第一电极（2A）和第一绝缘层（3）形成装置（10），其中在第二导电层（5）沉积之后，通过蚀刻剂除去第二绝缘层（4） 其相对于第二导电层（5）的材料是选择性的。 根据本发明，选择第一材料和第二材料材料，其仅相对于彼此被有限地可选择性地蚀刻，并且在沉积第二绝缘层（4）之前，另外的层（6）设置在第一绝缘体 层（3），其可相对于第一材料可选择性地蚀刻。 以这种方式，可以对绝缘层（3,4）施加氧化硅和氮化硅，因此根据本发明的方法与当前的IC工艺非常兼容。 优选通过蚀刻局部地去除第二绝缘层（4），然后通过蚀刻完全去除另外的层（6），最后通过蚀刻完全去除第二绝缘层（4）。

公开(公告)号：EP1770056B1

公开(公告)日：2015-11-11

申请号：EP06076692.0

申请日：2006-09-07

Applicant: Delphi Technologies, Inc.

Inventor： Chilcott, Dan W.

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81C1/00531 ,  B81B2203/033 ,  B81C2201/0132 ,  B81C2201/0142

公开(公告)号：EP1211219A3

公开(公告)日：2004-06-16

申请号：EP01128160.7

申请日：2001-11-27

Applicant: MICROSCAN SYSTEMS INCORPORATED ,  XEROX CORPORATION

Inventor： Scharf, Bruce R. ,  Kubby, Joel A. ,  Lin, Chuang-Chia ,  Tran, Alex T. ,  Zosel, Andrew J. ,  Gulvin, Peter M. ,  Chen, Jingkuang

IPC: B81B3/00

CPC classification number: B81C1/00484 ,  B81B2201/042 ,  B81B2203/0118 ,  B81C1/00666 ,  B81C2201/0142

Abstract: The present invention provides a micromechanical or microoptomechanical structure produced by a process comprising defining the structure in a single-crystal silicon layer separated by an insulator layer from a substrate layer; selectively etching the single crystal silicon layer; depositing and etching a polysilicon layer on the insulator layer, with remaining polysilicon forming mechanical elements of the structure; metalizing a backside of the structure; and releasing the formed structure.

公开(公告)号：EP1095401A1

公开(公告)日：2001-05-02

申请号：EP00931030.1

申请日：2000-04-26

Applicant: ROBERT BOSCH GMBH

Inventor： LAERMER, Franz ,  SCHILP, Andrea

IPC: H01L21/3065 ,  H01L21/66

CPC classification number: B81C1/00626 ,  B81C99/0065 ,  B81C2201/0132 ,  B81C2201/0142 ,  H01L21/3065 ,  H01L21/30655

Abstract: The invention relates to a method for the anisotropic etching of structures on a semiconductor body, in particular for etching recesses in a silicon body (18) which are defined laterally in a precise manner by an etching mask, using a plasma (28). An ion-accelerator voltage is applied to the semiconductor, at least during an etching step which continues for a predetermined period. Said ion-accelerator voltage is induced, in particular, by a high-frequency alternating current. The duration of the etching step is subdivided further into at least two etching periods, between which the applied ion-accelerator voltage is modified. A preferred embodiment contains two etching periods, whereby a higher accelerator voltage is used during the first etching period than during the second etching period. The duration of the first etching period can also be determined dynamically or statically during the etching steps using a device for detecting a polymer breakthrough. In addition, high frequency pulses or pulse packets with an adjustable pulse-pause ratio are preferably used to generate and adjust the level of the accelerator voltage.

公开(公告)号：EP2682363A1

公开(公告)日：2014-01-08

申请号：EP12175390.9

申请日：2012-07-06

Applicant: IMEC ,  NXP B.V.

Inventor： Boccardi, Guillaume ,  Du Bois, Bert

IPC: B81C1/00

CPC classification number: B81C1/00476 ,  B81B2201/0257 ,  B81C1/00595 ,  B81C2201/0132 ,  B81C2201/0142 ,  B81C2201/0177 ,  B81C2201/053

Abstract: The present invention is related to a method for producing a Micro-Electromechanical System (MEMS) device, comprising:
- Depositing a sacrificial oxide layer on a substrate,
- Depositing one or more structural layers on said sacrificial oxide layer and patterning said structural layers to form a structure,
- Removing the sacrificial layer by vapour etching,
to thereby release a portion of said structure,

wherein the step of depositing a sacrificial oxide layer comprises depositing a first layer (7) of a first sacrificial oxide having a first density, and depositing on said first layer a second layer (8) of a second sacrificial oxide, the second layer having a higher density than the first layer. The method allows to protect a first structural layer deposited on and in contact with the second sacrificial oxide layer, said vapour etching step having low selectivity of said first structural layer towards said first sacrificial oxide layer. Said first structural layer may be a silicon nitride layer protecting the backplate of a MEMS microphone.

Abstract translation: 本发明涉及一种用于制造微机电系统（MEMS）器件的方法，包括： - 在衬底上沉积牺牲氧化物层， - 在所述牺牲氧化物层上沉积一个或多个结构层，并将所述结构层图案化 形成结构， - 通过蒸汽蚀刻去除牺牲层，从而释放所述结构的一部分，其中沉积牺牲氧化物层的步骤包括沉积具有第一密度的第一牺牲氧化物的第一层（7），以及 在所述第一层上沉积第二牺牲氧化物的第二层（8），所述第二层具有比所述第一层更高的密度。 该方法允许保护沉积在第二牺牲氧化物层上并与第二牺牲氧化物层接触的第一结构层，所述蒸气蚀刻步骤具有所述第一结构层朝向所述第一牺牲氧化物层的低选择性。 所述第一结构层可以是保护MEMS麦克风的背板的氮化硅层。