公开(公告)号：KR1020090021728A

公开(公告)日：2009-03-04

申请号：KR1020070086489

申请日：2007-08-28

Applicant: 한국과학기술원

Inventor： 조성환 ,  장태광

IPC: H03M1/12

CPC classification number: H03M1/0621 ,  H03M1/20 ,  H03M2201/11 ,  H03M2201/6135 ,  H03M2201/625

Abstract: A VCO(Voltage Controlled Oscillator) and an analog-digital converter are provided to improve linearity and resolution by using a sub-feedback loop and a body bias voltage. An analog-digital converter includes a VCO(120) and a phase detector(130). The VCO includes a plurality of delay stages and a plurality of sub feedback stages. The plurality of delay stages form a main loop. The plurality of sub feedback stages are connected to the plurality of delay stages. The plurality of sub feedback stages form at least one or more sub feedback loops. The VCO outputs a plurality of oscillation signals from the output terminals of the plurality of delay stages in response to the input signal from the output terminal. The phase detector detects the phase shift amount of the plurality of oscillation signals. The phase detector determines the digital value corresponding to an input signal based on the phase shift amount.

Abstract translation: 提供VCO（压控振荡器）和模数转换器，以通过使用子反馈回路和体偏置电压来提高线性度和分辨率。 模数转换器包括VCO（120）和相位检测器（130）。 VCO包括多个延迟级和多个子反馈级。 多个延迟级形成主循环。 多个子反馈级连接到多个延迟级。 多个子反馈级形成至少一个或多个子反馈回路。 响应于来自输出端子的输入信号，VCO从多个延迟级的输出端输出多个振荡信号。 相位检测器检测多个振荡信号的相移量。 相位检测器基于相移量确定与输入信号对应的数字值。

公开(公告)号：KR1020020010973A

公开(公告)日：2002-02-07

申请号：KR1020000044340

申请日：2000-07-31

Applicant: 동부일렉트로닉스 주식회사

Inventor： 김석기 ,  성준제 ,  정재만 ,  정종덕

IPC: H03M1/20

CPC classification number: H03M1/14 ,  H03M1/18 ,  H03M1/205 ,  H03M2201/625

Abstract: PURPOSE: A folding A/D converter is provided to be capable of remarkably increasing resolution using a secondary folding part outputting secondary folding signals having cross points of same gaps from two adjacent ones of primary folding signals adjacent input levels of analog signals. CONSTITUTION: A plurality of folding parts(11-14) receives analog signals(Vin) to output first primary sine wave folding signals(F1-F4) having multiple cross points. A first comparator(20) compares the folding signals(F1-F4) with a reference voltage(Vref) to output first lower level signals(C-C4). A first encoder(30) encodes the first lower level signals(C-C4) to lower bit signals(B3,B4). An upper bit converter(40) compares the analog signals(Vin) with the reference signal(Vr) to output upper bit signals(B1,B2). A folding generator(100) outputs second folding signals(SF1-SF3) having cross points of same gaps from two adjacent ones of primary folding signals adjacent input levels of analog signals. A second comparator(200) outputs second lower level signals(CS1-CS3) by comparing the second folding signals(SF1-SF3) with the reference voltage(Vref). A second encoder(300) encodes the second lower level signals(CS1-CS3) to output lowest bit signals(B5,B6).

Abstract translation: 目的：提供一种折叠式A / D转换器，其能够使用次级折叠部分显着提高分辨率，所述次级折叠部分输出具有与相邻模拟信号输入电平相邻的主要折叠信号的相邻间隔相交的相交点的次级折叠信号。 构成：多个折叠部分（11-14）接收模拟信号（Vin）以输出具有多个交叉点的第一初级正弦波折叠信号（F1-F4）。 第一比较器（20）将折叠信号（F1-F4）与参考电压（Vref）进行比较，以输出第一低电平信号（C-C4）。 第一编码器（30）将第一低电平信号（C-C4）编码为低位信号（B3，B4）。 高位转换器（40）将模拟信号（Vin）与参考信号（Vr）进行比较以输出高位信号（B1，B2）。 折叠发生器（100）输出具有与相邻输入电平模拟信号相邻的主要折叠信号的相同间隙的交叉点的第二折叠信号（SF1-SF3）。 第二比较器（200）通过将第二折叠信号（SF1-SF3）与参考电压（Vref）进行比较来输出第二低电平信号（CS1-CS3）。 第二编码器（300）对第二较低电平信号（CS1-CS3）进行编码，以输出最低位信号（B5，B6）。

公开(公告)号：KR1020010096396A

公开(公告)日：2001-11-07

申请号：KR1020000020566

申请日：2000-04-19

Applicant: 학교법인 정석인하학원

Inventor： 윤광섭

IPC: H03M1/34

CPC classification number: H03M1/145 ,  H03M1/205 ,  H03M2201/625

Abstract: PURPOSE: An analog/digital converter using a folding multiplier is provided, which can perform a high speed driving and a low power consumption by designing two-step structure as maintaining a high resolution and a small chip area. CONSTITUTION: A reference voltage generator(13) generates a reference voltage if an analog input signal is inputted from the external, and a folding part(10) performs a preprocessing function with N pairs of full differential folding signals by receiving the analog input signal. An interpolation circuit(11) generates MxN pairs of digital signals according to an interpolation rate(M). A current comparator(12) outputs NxM circulation codes by receiving the digital signals from the interpolation circuit. An encoder(15) generates a binary weighted code. A current subtractor-amplifier circuit(14) recovers the digital signal into an analog signal through a current subtraction and converts into an input voltage signal of a corresponding block by performing the subtraction from the analog input signal. And a latch circuit(16) stores the binary weighted code from the encoder and at the same time outputs the digital signal of the uppermost 6 bit and the lowermost 6 bit to the external by being synchronized to an output applying signal.

Abstract translation: 目的：提供一种使用折叠倍增器的模拟/数字转换器，通过设计两级结构，保持高分辨率和小芯片面积，可实现高速驱动和低功耗。 构成：如果从外部输入模拟输入信号，参考电压发生器（13）产生参考电压，并且折叠部分（10）通过接收模拟输入信号来执行具有N对全差分折叠信号的预处理功能。 内插电路（11）根据内插速率（M）产生M×N对数字信号。 电流比较器（12）通过从内插电路接收数字信号来输出N×M循环码。 编码器（15）生成二进制加权码。 电流减法器放大器电路（14）通过电流减法将数字信号恢复为模拟信号，并通过执行模拟输入信号的减法将其转换为相应块的输入电压信号。 并且锁存电路（16）存储来自编码器的二进制加权码，同时通过与输出施加信号同步，将最上位6位和最低位6位的数字信号输出到外部。

公开(公告)号：KR1020010081238A

公开(公告)日：2001-08-29

申请号：KR1020000006437

申请日：2000-02-11

Applicant: 삼성전자주식회사

Inventor： 이상훈

IPC: H03M1/20

CPC classification number: H03M1/20 ,  H03M1/18 ,  H03M2201/625

Abstract: PURPOSE: An apparatus for improving the resolution of an A/D converter is provided to improve a resolution of an analog signal received from the outside without using an additional high resolution A/D converter. CONSTITUTION: An amplifier(30) amplifies an analog signal. An A/D converter(40) converts the amplified analog signal to a digital signal. A controller(50) converts the digital signal to a digital signal having an improved resolution and increases or decreases the digital signal as much as a predetermined value. A D/A converter(60) converts the digital signal outputted from the controller(50) to an analog signal. A subtracter(20) obtains a difference between the analog signal outputted from the D/A converter(60) and an analog from received the outside.

Abstract translation: 目的：提供一种用于提高A / D转换器分辨率的装置，以提高从外部接收的模拟信号的分辨率，而不使用附加的高分辨率A / D转换器。 构成：放大器（30）放大模拟信号。 A / D转换器（40）将放大的模拟信号转换成数字信号。 控制器（50）将数字信号转换成具有改善的分辨率的数字信号，并将数字信号增加或减少多达预定值。 D / A转换器（60）将从控制器（50）输出的数字信号转换为模拟信号。 减法器（20）获得从D / A转换器（60）输出的模拟信号与从外部接收的模拟信号之间的差。

公开(公告)号：KR101379301B1

公开(公告)日：2014-03-28

申请号：KR1020130017372

申请日：2013-02-19

Applicant: 주식회사 아진엑스텍

Inventor： 하상민 ,  원종백 ,  김창호 ,  최성혁 ,  이상태

IPC: H03M1/66

CPC classification number: H03M1/661 ,  H03M1/662 ,  H03M2201/6185 ,  H03M2201/625

Abstract: The present invention relates to a high-resolution digital-to-analog converter and a control method therefor. More particularly, the present invention relates to a digital-to-analog converter which increases a resolution using a interpolation method without using analog signal synthesis and a control method therefor. A method for generating high-resolution analog signals which relates to an embodiment of the present invention includes: a step of inputting first digital information; a step of shifting a bit of the first digital information by a predetermined bit; a step of moving the shifted first digital information to a first digital-to-analog converter (DAC) register; a step of inputting second digital information; a step of moving the shifted first digital information to a second DAC register, shifting the second digital information by the predetermined bit and moving the shifted second digital information to the first DAC register according to a synchronous signal; a step of inputting third digital information; a step of extracting the third digital information shifted by the predetermined bit using the first digital information, second digital information, shifted first digital information, shifted second digital information and interpolation method; and a step of outputting the generated analog information using the shifted third digital information. [Reference numerals] (AA) Start; (BB) End; (S100) Step of inputting first digital information of a predetermined bit; (S200) Step of shifting bit of the first digital information; (S300) Step of moving the shifted first digital information to a first DAC register; (S400) Step of moving the shifted first digital information to a second DAC register, shifting the second digital information by the predetermined bit and moving the shifted second digital information to the first DAC register according to a synchronous signal; (S500) Step of moving the shifted first digital information to a third DAC register, moving the shifted second digital information to the second DAC register, shifting third digital information and moving the shifted third digital information to the first DAC register; (S600) Step of obtaining output information having a higher resolution using the first, second, third digital information and the shifted first, second and third digital information; (S700) Step of outputting analog information using the output information

Abstract translation: 本发明涉及一种高分辨率数模转换器及其控制方法。 更具体地说，本发明涉及使用不使用模拟信号合成的内插方法提高分辨率的数/模转换器及其控制方法。 一种与本发明实施例相关的高分辨率模拟信号的产生方法，包括：输入第一数字信息的步骤; 将第一数字信息的一位移位预定位的步骤; 将移位的第一数字信息移动到第一数模转换器（DAC）寄存器的步骤; 输入第二数字信息的步骤; 将移位的第一数字信息移动到第二DAC寄存器，将第二数字信息移位预定位并根据同步信号将移位的第二数字信息移动到第一DAC寄存器的步骤; 输入第三数字信息的步骤; 使用第一数字信息，第二数字信息，移位的第一数字信息，移位的第二数字信息和插值方法提取由预定位移位的第三数字信息的步骤; 以及使用所移动的第三数字信息输出所生成的模拟信息的步骤。 （附图标记）（AA）开始; （BB）结束; （S100）输入预定位的第一数字信息的步骤; （S200）移位第一数字信息的位的步骤; （S300）将移位的第一数字信息移动到第一DAC寄存器的步骤; （S400）将移位的第一数字信息移动到第二DAC寄存器，将第二数字信息移位预定位并根据同步信号将移位的第二数字信息移动到第一DAC寄存器的步骤; （S500）将移位的第一数字信息移动到第三DAC寄存器，将移位的第二数字信息移动到第二DAC寄存器，移位第三数字信息并将移位的第三数字信息移动到第一DAC寄存器的步骤; （S600）使用第一，第二，第三数字信息和移位的第一，第二和第三数字信息获得具有较高分辨率的输出信息的步骤; （S700）使用输出信息输出模拟信息的步骤

公开(公告)号：KR101291341B1

公开(公告)日：2013-07-30

申请号：KR1020130001713

申请日：2013-01-07

Applicant: 주식회사 하이드로넷

Inventor： 임우석 ,  김상훈 ,  이준형

IPC: H03M1/12

CPC classification number: H03M1/20 ,  H03M1/123 ,  H03M1/361 ,  H03M2201/194 ,  H03M2201/2216 ,  H03M2201/6185 ,  H03M2201/625

Abstract: PURPOSE: A resolution improving device and a method thereof using an analog to digital converter port inside a MCU are provided to improve the resolution of an analog signals inputted from outside. CONSTITUTION: A resolution improving device of an analog to digital converter (ADC) comprises a bisectional unit (110), an adding device (120), and a MCU (130). The bisectional part divides an analog input signal into 2 halves for outputting the signal of a sub part. The adding device adds the analog input signal to the signal of the sub part which is outputted from the bisectional part for outputting. The MCU receives the analog input signal through a first ADC port and receives the main part signal of the signal divided into 2 halves through a second ADC port or an input and output port. The MCU converts the main part signal into a digital signal when a signal is inputted through the input and output port and assigns 1 to an additional bit above the most significant bit for outputting. The MCU converts the analog signal into the digital signal when a signal is not inputted through the input and output port and assigns 0 to the additional bit above the most significant bit for outputting. [Reference numerals] (110) Bisection of a signal; (120) Adding device; (AA) Input signal; (BB) Upper signal of the bisectional signal

Abstract translation: 目的：提供一种分辨率改进装置及其在MCU内使用模数转换器端口的方法，以提高从外部输入的模拟信号的分辨率。 构成：模数转换器（ADC）的分辨率改善装置包括二分单元（110），加法装置（120）和MCU（130）。 二等分部分将模拟输入信号分成两半，用于输出子部分的信号。 添加装置将模拟输入信号添加到从二分割部分输出的子部分的信号以进行输出。 MCU通过第一个ADC端口接收模拟输入信号，并通过第二个ADC端口或输入和输出端口将信号的主要部分信号分为两半。 当通过输入和输出端口输入信号时，MCU将主要部分信号转换为数字信号，并将1分配给高于最高有效位以用于输出。 当信号不通过输入和输出端口输入时，MCU将模拟信号转换为数字信号，并将0分配给最高有效位以上的附加位进行输出。 （附图标记）（110）信号的二等分; （120）添加设备; （AA）输入信号; （BB）二分信号的上位信号

公开(公告)号：KR1020080047192A

公开(公告)日：2008-05-28

申请号：KR1020060117226

申请日：2006-11-24

Applicant: 한국과학기술원

Inventor： 조성환 ,  김재욱

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03M1/20 ,  H03M2201/625 ,  H03M2201/71

Abstract: A method for converting analog to digital with enhanced resolution by oversampling is provided to improve resolution by using a voltage controlled oscillator to quantize an analog signal and determining a digital code to be outputted by giving weighted values to various analog values after sampling the various analog values for one cycle of a reference clock. A method for converting analog to digital with enhance resolution by oversampling includes the steps of: generating an oversampling clock having a frequency N times more than a reference clock(S200); converting M analog input signals into M digital values(S400) after sampling and quantizing the M analog input signals for each cycle of the reference clock by being synchronized with the oversampling clock(S300); determining a weighted value for each of the M digital values(S600); and determining one digital code on the basis of the M digital values and the weighted value(S700).

Abstract translation: 提供了通过过采样将模拟转换为数字增强分辨率的方法，通过使用压控振荡器来量化模拟信号并通过在对各种模拟值进行采样之后给予各种模拟值的加权值来确定要输出的数字码来确定要输出的数字码，以提高分辨率 用于参考时钟的一个周期。 一种通过过采样将模拟转换为数字增强分辨率的方法包括以下步骤：产生具有比参考时钟N倍的频率的过采样时钟（S200）; 通过与过采样时钟同步（S300）对参考时钟的每个周期对M个模拟输入信号进行采样和量化后，将M个模拟输入信号转换为M个数字值（S400）。 确定每个M个数字值的加权值（S600）; 并根据M个数字值和加权值确定一个数字代码（S700）。

公开(公告)号：KR1020070094162A

公开(公告)日：2007-09-20

申请号：KR1020060024446

申请日：2006-03-16

Applicant: 엘에스산전 주식회사

Inventor： 홍상우

IPC: H03M1/12

CPC classification number: H03M1/186 ,  H03M1/127 ,  H03M1/20 ,  H03M2201/6107 ,  H03M2201/625

Abstract: A method of adjusting a resolution for digital data is provided to increase the resolution of the digital data in a restricted section by applying a neural network scheme on the digital data. A range of a digital value, which is to be converted, is determined. A range of a digital input value is determined corresponding to the digital value. A predetermined resolution is determined by the range of the digital value and the range of the digital input value. A relation between the input data and the output data is determined based on a neural network algorithm according to the determined resolution. The resolution has a relation of 1 by 1 or N by N. The neural network algorithm uses a multilayered perception structure.

Abstract translation: 提供一种调整数字数据分辨率的方法，通过在数字数据上应用神经网络方案来增加限制部分中数字数据的分辨率。 确定要转换的数字值的范围。 根据数字值确定数字输入值的范围。 预定分辨率由数字值的范围和数字输入值的范围确定。 根据所确定的分辨率，基于神经网络算法确定输入数据与输出数据之间的关系。 该分辨率具有1乘1或N与N的关系。神经网络算法使用多层感知结构。

公开(公告)号：KR1020070076111A

公开(公告)日：2007-07-24

申请号：KR1020060005123

申请日：2006-01-17

Applicant: 엘지전자 주식회사

Inventor： 김세원 ,  김상진

IPC: H03M1/12

CPC classification number: H03M1/203 ,  H03M1/123 ,  H03M2201/1172 ,  H03M2201/2216 ,  H03M2201/6185 ,  H03M2201/625

Abstract: A multi channel analog-digital converting apparatus is provided to reduce the size of apparatus and cost by forming a channel group composed of a sampling switch with low resolution and a channel group composed of a sampling switch with high resolution. A multi channel analog-digital converting apparatus includes a first channel group(10), a second channel group(20), and a group sampling switch(30). The first channel group(10) is composed of sampling switches of a predetermined number of channels having first resolution. The second channel group(20) is composed of sampling switches of a predetermined number of channels having second resolution. One side of the group sampling switch(30) is connected with the output of the second channel group(20), and the other side thereof is connected with the output of the first channel group(10).

Abstract translation: 提供一种多通道模拟数字转换装置，通过形成由低分辨率的采样开关构成的通道组和由高分辨率的采样开关组成的通道组来减小设备的尺寸和成本。 多通道模拟数字转换装置包括第一通道组（10），第二通道组（20）和组采样开关（30）。 第一通道组（10）由具有第一分辨率的预定数量的通道的采样开关组成。 第二通道组（20）由具有第二分辨率的预定数量的通道的采样开关组成。 组采样开关（30）的一侧与第二通道组（20）的输出端连接，另一侧与第一通道组（10）的输出端连接。

公开(公告)号：KR1020060099023A

公开(公告)日：2006-09-19

申请号：KR1020050019997

申请日：2005-03-10

Applicant: 엘지전자 주식회사

Inventor： 이우열

IPC: H03M1/12 ,  H03M1/10

CPC classification number: H03M1/0621 ,  H03M1/1023 ,  H03M1/12 ,  H03M2201/615 ,  H03M2201/625

Abstract: 본 발명은 아날로그 그래픽 신호를 해상도에 따라 아날로그/디지털 변환기가 정확히 디지털 그래픽신호로 변환할 수 있도록 오프셋 값을 설정한다.
미리 설정된 오프셋 조절용 기준신호를 통과시키는 커플링 콘덴서와, 상기 커플링 콘덴서를 통과한 신호를 디지털 신호로 변환하는 아날로그/디지털 변환기와, 상기 아날로그/디지털 변환기의 출력신호와, 아날로그 그래픽 신호의 해상도에 따라 설정되는 기준 오프셋 값을 비교하고, 비교 결과에 따라 충전 제어신호 또는 방전 제어신호를 선택적으로 발생하는 비교기와, 상기 충전 제어신호 또는 방전 제어신호에 따라 오프셋 전압을 증가 또는 감소시켜 상기 콘덴서에 인가하는 차지 펌프로 구성되는 것으로서 아날로그 그래픽 신호를 해상도에 따라 정확히 10비트 또는 12비트의 디지털 그래픽 신호로 변환하여 평판 표시패널에 표시되는 그래픽 신호의 화질이 향상된다.
ADC.아날로그/디지털 변환, 오프셋, 그래픽신호, 차지펌프