公开(公告)号：WO2013097126A1

公开(公告)日：2013-07-04

申请号：PCT/CN2011/084870

申请日：2011-12-29

Applicant: 广东生益科技股份有限公司 ,  苏民社 ,  刘潜发

Inventor： 苏民社 ,  刘潜发

IPC: H05K1/03 ,  H05K3/00 ,  B32B15/04 ,  B32B17/06 ,  B32B7/12

CPC classification number: H05K1/0271 ,  B32B3/20 ,  B32B15/08 ,  B32B27/20 ,  B32B27/281 ,  B32B27/283 ,  B32B27/285 ,  B32B27/302 ,  B32B27/32 ,  B32B27/322 ,  B32B27/36 ,  B32B27/38 ,  B32B27/42 ,  B32B2264/0257 ,  B32B2264/102 ,  B32B2264/104 ,  B32B2264/105 ,  B32B2264/108 ,  B32B2307/704 ,  B32B2307/734 ,  B32B2457/00 ,  H05K1/0306 ,  H05K3/022 ,  H05K3/386 ,  H05K3/4611 ,  H05K2201/0137 ,  Y10T156/1056 ,  Y10T428/249982 ,  Y10T428/249985

Abstract: 一种电路基板，包括玻璃占有的体积百分率为45%以上的多空隙的玻璃膜、分别位于所述玻璃膜两侧的树脂粘接层、以及位于所述树脂粘接层外侧的金属箔，所述玻璃膜、树脂粘接层及金属箔通过压制结合在一起，所述树脂粘接层的树脂填充于玻璃膜的空隙中。该电路基板采用多空隙的玻璃膜为载体材料，使得树脂粘接层与玻璃膜表面具有良好的结合力，并使电路基板的X、Y方向的CTE与原来相比得到了降低，以及具有良好的成型性，工艺操作简便。此外，还提供一种制作所述电路基板的制作方法。

公开(公告)号：WO2015055829A1

公开(公告)日：2015-04-23

申请号：PCT/EP2014/072347

申请日：2014-10-17

Applicant: APPLIED MATERIALS, INC. ,  MORRISON, Neil ,  DEPPISCH, Thomas ,  LOTZ, Hans-Georg

Inventor： MORRISON, Neil ,  DEPPISCH, Thomas ,  LOTZ, Hans-Georg

IPC: G06F3/041 ,  G06F3/044

CPC classification number: G06F3/03547 ,  G06F3/041 ,  G06F3/044 ,  G06F2203/04103 ,  H05K1/0274 ,  H05K1/0306 ,  H05K2201/0137 ,  H05K2201/0145

Abstract: A layer stack (100; 200) for a touch panel is described. The layer stack includes a substrate (110; 210) including a polymer for depositing one or more layers on the substrate; a patterned transparent conductive oxide (TCO) layer (160; 260) provided over the substrate (110; 210), which comprises areas of TCO and gaps between the areas of TCO; a first dielectric material (170; 270) provided in the gaps of the patterned TCO layer (160; 260); and a dielectric layer (180; 280) being deposited directly on the TCO areas of the TCO layer (160; 260) and directly on the first dielectric material (170; 270). Further, a touch panel including a layer stack and a method for forming a layer stack for a touch panel is described.

Abstract translation: 描述了用于触摸面板的层叠体（100; 200）。 所述层叠层包括：衬底（110; 210），其包括用于在所述衬底上沉积一层或多层的聚合物; 设置在衬底（110; 210）上的图案化的透明导电氧化物（TCO）层（160; 260），其包括TCO的区域和TCO的区域之间的间隙; 设置在所述图案化TCO层（160,260）的间隙中的第一介电材料（170; 270）; 以及直接在所述TCO层（160,260）的TCO区域上并且直接沉积在所述第一介电材料（170; 270）上的电介质层（180; 280）。 此外，描述了包括层堆叠的触摸面板和用于形成用于触摸面板的层叠体的方法。

公开(公告)号：WO2014002529A1

公开(公告)日：2014-01-03

申请号：PCT/JP2013/055415

申请日：2013-02-28

Applicant: 石原薬品株式会社

Inventor： 川戸　祐一 ,  三田　倫広 ,  前田　祐介 ,  工藤　富雄

IPC: H05K3/38 ,  H05K1/09 ,  H05K3/24

CPC classification number: H05K3/38 ,  H05K1/0296 ,  H05K1/0313 ,  H05K1/097 ,  H05K3/245 ,  H05K3/246 ,  H05K3/386 ,  H05K2201/0129 ,  H05K2201/0137 ,  H05K2201/0154 ,  H05K2201/032 ,  H05K2203/1126 ,  H05K2203/1131 ,  Y10T29/49163

Abstract: 　銅微粒子から成る皮膜を光焼成して形成される導電膜において、導電膜の基材への密着性を向上する。　回路基板１は、導電膜２を有する回路と基板３とを備えたものである。回路基板１は、基板３と導電膜２との間に樹脂層４をさらに備える。基板３は、非熱可塑性の基材３１から成る。樹脂層４は、熱可塑性樹脂を含有する。導電膜２は、銅微粒子２１から成る皮膜を光焼成して形成される。これにより、導電膜２は、樹脂層４を介して基材３１への密着性が向上する。

Abstract translation: 为了提高导电膜对基材的粘附性，所述导电膜是通过对由细铜颗粒形成的涂膜进行光烧制而形成的。 电路板（1）具有：具有导电膜（2）的电路; 和基板（3）。 电路板（1）还在基板（3）和导电膜（2）之间设置有树脂层（4）。 基材（3）由不是热塑性的基材（31）形成。 树脂层（4）含有热塑性树脂。 导电膜（2）通过将由细铜颗粒（21）形成的涂膜进行光烧制而形成。 因此，通过树脂层（4）改善了导电膜（2）与基体（31）的粘合性。

公开(公告)号：US20180263117A1

公开(公告)日：2018-09-13

申请号：US15810800

申请日：2017-11-13

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravindranath V. Mahajan ,  James C. Matayabas, JR. ,  Johanna M. Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Kamgaing ,  Adel A. Elsherbini ,  Kemal Aygun

IPC: H05K1/18 ,  H01L23/00

CPC classification number: H05K1/189 ,  G06F1/163 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H05K1/0393 ,  H05K1/181 ,  H05K1/185 ,  H05K13/0469 ,  H05K2201/0137 ,  H05K2203/1469 ,  Y10T29/49146 ,  H01L2924/00

Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.

公开(公告)号：US09999130B2

公开(公告)日：2018-06-12

申请号：US15258330

申请日：2016-09-07

Applicant: Hisense Broadband Multimedia Technologies Co., Ltd.

Inventor： Wei Zhao ,  Wei Cui ,  Lin Yu

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H05K1/18 ,  H05K1/0298 ,  H05K1/117 ,  H05K3/3452 ,  H05K2201/0137 ,  H05K2201/10121

Abstract: The application provides a printed circuit board and an optical module so as to alleviate poor contact between the electro-conductive contact sheet group and the clamping piece due to the solder resist. The printed circuit board includes a substrate, and electro-conductive wirings and electro-conductive contact sheet group both laid on the surface of the substrate, where the substrate is overlaid with solder resist, and the solder resist has no contact with the electro-conductive contact sheet group.

公开(公告)号：US20170228055A1

公开(公告)日：2017-08-10

申请号：US15494800

申请日：2017-04-24

Applicant: Sinovia Technologies

Inventor： Whitney GAYNOR ,  George BURKHARD

IPC: G06F3/041 ,  G03F1/24 ,  H01B5/14 ,  B05D3/00 ,  H01B13/00 ,  H01B1/22

CPC classification number: G06F3/041 ,  B05D3/007 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y40/00 ,  G03F1/24 ,  G03F7/0002 ,  G03F7/0047 ,  G03F7/038 ,  G03F7/0388 ,  G03F7/161 ,  G06F3/044 ,  G06F2203/04103 ,  H01B1/22 ,  H01B5/14 ,  H01B13/0013 ,  H01L51/444 ,  H01L51/5203 ,  H05K1/0271 ,  H05K1/0274 ,  H05K1/036 ,  H05K1/09 ,  H05K3/103 ,  H05K2201/0108 ,  H05K2201/0137 ,  H05K2203/10 ,  Y10T428/24355 ,  Y10T442/188 ,  Y10T442/191

Abstract: A method of fabricating a composite conductive film is provided. The method includes providing, as a matrix, a layer of cross-linkable polymer, where the cross-linkable polymer is in a non-cross-linked state. The method further includes introducing inorganic nanowires upon a surface of the layer of cross-linkable polymer. The inorganic nanowires are, in isolated form, characterized by a first conductivity stability temperature. The method further includes embedding at least some of the inorganic nanowires into the layer of cross-linkable polymer to form an inorganic mesh, thereby forming the composite conductive film. The method further includes cross-linking the polymer within a surface portion of the composite conductive film. Cross-linking the polymer within the surface portion of the composite conductive film results in the surface portion having a second conductivity stability temperature that is greater than the first conductivity stability temperature.

公开(公告)号：US09652055B2

公开(公告)日：2017-05-16

申请号：US14142036

申请日：2013-12-27

Applicant: APPLIED MATERIALS, INC.

Inventor： Neil Morrison ,  Thomas Deppisch ,  Hans-Georg Lotz

IPC: H05K1/03 ,  G06F3/044 ,  G06F3/0354 ,  G06F3/041 ,  H05K1/02

CPC classification number: G06F3/03547 ,  G06F3/041 ,  G06F3/044 ,  G06F2203/04103 ,  H05K1/0274 ,  H05K1/0306 ,  H05K2201/0137 ,  H05K2201/0145

Abstract: A layer stack for a touch panel is described. The layer stack includes a substrate including a polymer for depositing one or more layers on the substrate; a patterned transparent conductive oxide (TCO) layer provided over the substrate, which comprises areas of TCO and gaps between the areas of TCO; a first dielectric material provided in the gaps of the patterned TCO layer and a dielectric layer being deposited directly on the TCO areas of the TCO layer and directly on the first dielectric material. Further, a touch panel including a layer stack and a method for forming a layer stack for a touch panel is described.

公开(公告)号：US20150156887A1

公开(公告)日：2015-06-04

申请号：US14209143

申请日：2014-03-13

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Ji Sung Cho ,  Toshiko Yokota ,  Makoto Dobashi ,  Jin Gu Kim ,  Ichiro Ogura ,  Je Hong Kyoung

IPC: H05K3/02 ,  H05K1/09

CPC classification number: H05K3/022 ,  H05K1/09 ,  H05K3/16 ,  H05K2201/0137 ,  H05K2201/032 ,  H05K2201/0338 ,  Y10T428/12569

Abstract: Disclosed herein are a method of forming an amorphous alloy film and a printed wiring board manufactured by the same. The amorphous alloy film may be formed on a copper foil as one of rust-proofing treatment methods of the copper foil to thereby simultaneously show and improve corrosion-resistance and conductivity, and the amorphous alloy film may be formed by the sputtering deposition method, such that high melting point materials may be manufactured as a thin film at a relatively low temperature and the amorphous alloy film having strong adhesion strength with a substrate may be obtained.

Abstract translation: 本文公开了形成非晶合金膜的方法和由其制造的印刷线路板。 非晶合金膜可以形成在铜箔上作为铜箔的防锈处理方法之一，从而同时显示并提高耐腐蚀性和导电性，并且非晶合金膜可以通过溅射沉积法形成，例如 可以在相对低的温度下制造高熔点材料作为薄膜，并且可以获得与基板具有强粘合强度的非晶态合金膜。

公开(公告)号：US20150109748A1

公开(公告)日：2015-04-23

申请号：US14360906

申请日：2011-11-29

Applicant: Zhongyao Yu ,  Xia Zhang

Inventor： Zhongyao Yu ,  Xia Zhang

IPC: H05K1/18 ,  H05K3/46 ,  H01L21/78 ,  H05K1/11 ,  H01L25/00 ,  H01L25/16

CPC classification number: H05K1/188 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24135 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/92144 ,  H01L2924/12042 ,  H05K1/115 ,  H05K1/185 ,  H05K3/46 ,  H05K3/4652 ,  H05K2201/0137 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2201/09509 ,  H01L2924/00

Abstract: An active chip package substrate and a method for preparing the same. The active chip package substrate includes: a core board; at least one upper active chip, embedded in the core board and having an active surface facing toward a lower surface of the core board, the upper active chip being an active bare chip; and at least one lower active chip, embedded in the core board and having an active surface facing toward an upper surface of the core board, the lower active chip being an active bare chip.

Abstract translation: 一种有源芯片封装基板及其制备方法。 有源芯片封装基板包括：芯板; 至少一个上有源芯片，嵌入在所述芯板中并且具有面向所述芯板的下表面的有源表面，所述上有源芯片是有源裸芯片; 以及至少一个下部有源芯片，嵌入在所述芯板中并且具有面向所述芯板的上表面的有源表面，所述下部有源芯片是有源裸芯片。

公开(公告)号：US20150047882A1

公开(公告)日：2015-02-19

申请号：US14380981

申请日：2013-02-26

Applicant: APPLIED NANOTECH HOLDINGS, INC.

Inventor： Nan Jiang ,  Zvi Yaniv

IPC: H05K1/05 ,  H05K1/02 ,  H05K3/12 ,  H05K1/09

CPC classification number: H05K1/053 ,  C04B41/009 ,  C04B41/52 ,  C04B41/90 ,  C04B2111/00844 ,  H01L23/373 ,  H01L2924/0002 ,  H05K1/0284 ,  H05K1/09 ,  H05K1/181 ,  H05K3/12 ,  H05K2201/0104 ,  H05K2201/0137 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/06 ,  H05K2201/10106 ,  H01L2924/00 ,  C04B35/522 ,  C04B41/4539 ,  C04B41/5001 ,  C04B41/5031 ,  C04B41/5089 ,  C04B41/5059 ,  C04B41/5092 ,  C04B41/522 ,  C04B41/5063 ,  C04B41/5064 ,  C04B41/4535 ,  C04B41/4572 ,  C04B41/5127

Abstract: Different kinds of printing pastes or inks are utilized in various combinations to develop multiple ceramic dielectric layers on graphitic substrates in order to create effective dielectric ceramic layers that combine good adhesion to both graphitic substrates and printed copper traces, and strong insulating capability. The pastes or inks may comprise a high thermal conductivity powder.

Abstract translation: 不同种类的印刷浆料或油墨被用于各种组合以在石墨基材上形成多个陶瓷电介质层，以便产生有效的介电陶瓷层，其与石墨基材和印刷的铜迹线具有良好的粘合性，并具有很强的绝缘性能。 糊剂或油墨可以包含高导热性粉末。