公开(公告)号：EP1570496B1

公开(公告)日：2008-05-14

申请号：EP03721372.5

申请日：2003-03-14

Applicant: Bourns, Inc.

Inventor： BURKE, Ray ,  O'BRIEN, Maurice ,  LAN, Poting ,  CHU, Stelar

IPC: H01C1/14 ,  H01C7/02

CPC classification number: H01C7/027 ,  H01C1/1406 ,  H01C1/148 ,  H01C7/02 ,  H01C17/28 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/429 ,  H05K3/44 ,  H05K3/445 ,  H05K2201/09181 ,  H05K2201/09554 ,  H05K2201/09845

Abstract: An electronic device is manufactured using printed circuit board manufacturing processes. In particular, a laminar device comprises a first metal layer (12), a second metal layer (14), at least one layer of device material sandwiched between the first and second metal layers. A first layer of insulating material (40) substantially covers the first metal layer (12). A third metal layer (48) is provided on the first layer of insulating material (40). This third metal layer (48) is divided to provide a first terminal (90) and a second terminal (92). The first terminal (90) is electrically connected to the first metal layer (12) by a conductive interconnect (84) formed through said first layer of insulating material (40), and the second terminal (92) is electrically connected to said second metal layer (14) by a conductive path (68) comprising an insulated conductive channel which passes through and is insulated from said first metal layer (12) and said at least one layer of device material (16). The use of an insulated channel provides a cost effective method of manufacture and maximizes the effective area of device material used. A PTC component is built through this method.

公开(公告)号：EP1662778B1

公开(公告)日：2008-03-05

申请号：EP05257354.0

申请日：2005-11-30

Applicant: Psion Teklogix Systems Inc.

Inventor： Kricorissian, Gregg ,  Zhang, Tao

IPC: H04N5/225 ,  H05K1/14

CPC classification number: H04N5/2253 ,  H04N5/2256 ,  H05K1/116 ,  H05K1/144 ,  H05K3/3405 ,  H05K3/366 ,  H05K3/368 ,  H05K3/403 ,  H05K2201/048 ,  H05K2201/09145 ,  H05K2201/09181 ,  H05K2201/09481 ,  H05K2201/10287 ,  H05K2201/2072 ,  H05K2203/128 ,  Y10T29/49144 ,  Y10T29/49169

公开(公告)号：EP0720232B1

公开(公告)日：2007-04-11

申请号：EP94927045.8

申请日：1994-09-14

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： YAMAGUCHI, Masayoshi 2-22, Nishimachi 1-chome ,  SAWANO, Mitsutoshi 13-23, Soshigaya 3-chome ,  HOHKI, Kazutoshi 20-6, Higashi-Toyoda 3-chome

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/16 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L23/24 ,  H01L23/5385 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H05K1/141 ,  H05K1/147 ,  H05K3/3442 ,  H05K3/368 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/09181 ,  H05K2201/09536 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Bare chips (201 to 203) are mounted on regions (101 to 103) of a printed wiring board (100), respectively. The chips are soldered to a motherboard at external electrode pads (105) on their borders. Lead pads (107) and the external electrode pads (105) are interconnected through a circuit pattern (109), through-holes (111) and interstitial via-holes (112). A circuit pattern (109) is disposed on a die bonding surface of the bare IC chips (201, 202) for which insulation is not necessary. A multi-chip module is thus completed.

公开(公告)号：EP1729555A1

公开(公告)日：2006-12-06

申请号：EP05011726.6

申请日：2005-05-31

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： Fischer, Alfred ,  Gubisch, Thomas ,  Niebler, Günther ,  Teichrieb, Eugen

IPC: H05K3/36 ,  H05K1/14

CPC classification number: H05K3/366 ,  H05K3/0044 ,  H05K3/403 ,  H05K2201/048 ,  H05K2201/09036 ,  H05K2201/09181 ,  H05K2201/09645 ,  H05K2203/1476

Abstract: Bei dem Verfahren zur Herstellung einer ersten Leiterplatte (1) zur Aufnahme einer weiteren Leiterplatte (20) werden Kontaktierungsflächen (11 - 14) auf der ersten Leiterplatte (1) aufgebracht. Es wird eine schlitzförmige Öffnung (4) mit seitlichen Ausbuchtungen (7) in die erste Leiterplatte im Bereich der Kontaktierungsflächen (11-14) eingebracht, um eine Klemmleiste (25) der weiteren Leiterplatte (20) aufnehmen zu können. Die Innenseite (5) der schlitzförmigen Öffnung (4) wird mit einer leitfähigen Schicht (52) überzogen, so dass eine elektrische Verbindung mit den Kontaktierungsflächen (11 - 14) hergestellt wird. Die schlitzförmige Öffnung (9) wird soweit verbreitert, dass die leitfähige Schicht (52) nur noch in den Ausbuchtungen (7) enthalten ist. In einem alternativen Herstellungsverfahren wird anstelle einer Öffnung (4) eine Vertiefung (4') in eine zweite Leiterplatte (1') eingebracht. Dadurch kann die schlitzförmige Vertiefung (4') mit den seitlichen Ausbuchtungen (7) vorteilhaft in einem Arbeitsgang hergestellt werden. Die Vielzahl von Bohrungen zum Erhalt der Vielzahl von Löchern entfällt. Die Erfindung betrifft ferner Herstellungsverfahren für ein Leiterplattensystem sowie durch das Verfahren hergestellte Leiterplatten und Leiterplattensysteme.

Abstract translation: 该方法涉及形成在用于接收另一印刷电路板的端子条接触表面（11-14）的区域中的槽状的开口（4）具有横向突起（7）插入的印刷电路板英寸 开口的内侧涂覆有导电层上的电连接也是如此与所述表面制成。 开口变宽，求DASS模层中的突起被接收。 因此独立claimsoft包括用于印刷电路板系统，其包括印刷电路板。

公开(公告)号：EP1128714B9

公开(公告)日：2006-07-26

申请号：EP01301160.6

申请日：2001-02-09

Applicant: Agilent Technologies, Inc. (a Delaware corporation)

Inventor： Loh, Kah Phang

IPC: H05K1/14

CPC classification number: H01L31/0203 ,  H05K1/141 ,  H05K1/182 ,  H05K3/0052 ,  H05K3/3442 ,  H05K3/368 ,  H05K3/403 ,  H05K2201/09072 ,  H05K2201/09181 ,  H05K2201/10106 ,  H05K2201/10446

公开(公告)号：EP1020908B1

公开(公告)日：2006-03-22

申请号：EP98935341.2

申请日：1998-08-04

Applicant: TDK Corporation

Inventor： GOTOH, Masashi, TDK Corporation ,  KANAZAWA, Jitsuo, TDK Corporation ,  YAMAMOTO, Shuichiro, TDK Corporation

IPC: H01L23/12 ,  H03H9/02 ,  H03H9/10 ,  H03H9/25 ,  H05K1/11

CPC classification number: H05K3/403 ,  H01L23/10 ,  H01L23/49805 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16195 ,  H01L2924/3025 ,  H03H9/1071 ,  H05K3/0052 ,  H05K3/244 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/42 ,  H05K2201/09181 ,  H05K2201/10727 ,  H05K2203/0723 ,  H01L2224/0401

Abstract: Resin-sealed surface mounting type electronic parts which are formed in such a way that an electronic part element (5) is mounted on a resin-made wiring board (1) and a sealed area having a cavity housing the element (5) is formed by bonding a lid member to the board (1) so as to cover the element (5), and then side-face electrodes (21) are formed in through conductive grooves provided inside the bonding surface of the cap member on the board (1). Plated layers in the through conductive grooves have conductors (10 and 11) on the upper and lower surfaces of the board (1) each constituted of two or more kinds of metallic layers containing a plated gold layer (13) formed as the uppermost layer and a plated copper layer (12) and connected to the peripheral edges of the conductive grooves. On the upper conductor (10), however, only the plated copper layer (12) is formed and the other plated layers including the gold layer (13) are not formed on the conductor (10) so as to improve the reliability of the adhesion between the board (1) and cap member. Therefore, the reliability of the adhesion between the board (1) and the cap member for forming the sealed area having a cavity housing the element (5) is improved and the reliability of the airtight sealing of the element (5) is improved.

公开(公告)号：EP1534054A2

公开(公告)日：2005-05-25

申请号：EP04027251.0

申请日：2004-11-17

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Kimura, Junichi ,  Nishii, Toshihiro ,  Ochi, Akio ,  Harada, Shinji

IPC: H05K1/18 ,  H05K3/46 ,  H01L23/538

CPC classification number: H05K1/165 ,  H01L21/50 ,  H01L24/97 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12034 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/186 ,  H05K3/0052 ,  H05K3/3405 ,  H05K3/403 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/086 ,  H05K2201/09181 ,  H05K2201/10371 ,  H05K2203/0169 ,  H05K2203/0191 ,  H05K2203/0568 ,  H05K2203/063 ,  Y10T156/1052 ,  Y10T156/1057 ,  Y10T156/12 ,  H01L2924/00

Abstract: The object of the present invention is to provide a laminated circuit board with electronic components buried therein wherein the laminated circuit board may assure excellent reliability of electrical connections and high mechanical strength even with electronic components mounted in high density. It comprises a substrate (1001) on which a land disposed on one main surface thereof is connected and fixed by solder (1007) to integrated circuit (1005) or the like, and a sheet (1011) laminated on the upper surface of the substrate (1001) and also provided with a filling portion by fluid resin formed by clearance (1008) at the outer periphery of integrated circuit (1005) or the like, wherein the sheet (1011) maintains its shape by woven or non-woven cloth having a hole (1012) in which integrated circuit (1005) or the like is buried, and the woven or non-woven cloth is impregnated with resin (1016) having heat fluidity and is thermally compressed. Thus, the electrical and mechanical connections between the laminated circuit board and electronic component can be enhanced in reliability.

Abstract translation: 本发明的目的是提供一种层压电路板在其中具有埋worin层压电路板可以保证电连接，甚至与安装在高密度电子元件高的机械强度的可靠性优异的电子部件。 它包括其上一个国家设置在一个主表面上被连接，并通过焊接（1007）固定在基板（1001），以层叠在基片的上表面上的集成电路（1005）等，以及片材（1011） （1001），并因此提供有通过在集成电路（1005）或类似的外周通过的间隙（1008）形成的流体树脂的填充部，worin片（1011）由具有纺织或无纺布保持其形状 其中空穴（1012）集成电路（1005）等被埋入和织造或非织造布中含浸有树脂（1016），其具有热流动性和热压缩。 因此，层叠电路板和电子元件之间的电气和机械连接可在可靠性被增强。

公开(公告)号：EP1484950A2

公开(公告)日：2004-12-08

申请号：EP04008025.1

申请日：2004-04-01

Applicant: Novar GmbH

Inventor： Gernhardt, Angelika ,  Goulet, Thomas ,  Menzel, Carsten ,  Ollik, Waldemar

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K3/403 ,  H05K1/0284 ,  H05K3/0052 ,  H05K3/3405 ,  H05K3/3442 ,  H05K3/368 ,  H05K3/42 ,  H05K2201/09118 ,  H05K2201/09181 ,  H05K2201/09481 ,  H05K2201/10666 ,  H05K2203/0455 ,  Y02P70/613 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T29/49789

Abstract: Ein Verfahren zur Kontaktierung der Leiterbahnen einer Schaltungsplatine (1) mit den Leiterbahnen eines Bauteiles (10) in MID-Technologie umfasst folgende Schritte:

Auf dem Nutzen, aus dem die Schaltungsplatine gewonnen wird, werden die Leiterbahnen mindestens bis zum Rand der Schaltungsplatine geführt.
Längs dieses Randes wird der Nutzen im Bereich der Leiterbahnen mit Durchgangsbohrungen (6d) versehen.
Die Durchgangsbohrungen werden galvanisch durchkontaktiert.
Die aus dem Nutzen herausgetrennte Schaltungsplatine wird relativ zu dem MID-Bauteil so positioniert, dass die aneinander grenzenden Leiterbahnen von Schaltungsplatine und MID-Bauteil miteinander verlötbar sind.

Zweckmäßig erhält die Schaltungsplatine deckungsgleich zu den an ihrem Rand endenden Leiterbahnen rückseitig elektrische Kontaktierungsflächen (6b), welche über metallisierte und durchkontaktierte Bohrungen mit den vorderseitigen Leiterbahnen (5) elektrisch verbunden sind.

Abstract translation: 该方法包括以前者中的布局制造电路板（1）的导电轨道（5），其中轨道延伸超过限定稍后面向MID部件（10）的边缘的分隔线，提供通过 至少在轨道区域沿着分离线的孔（6d），电穿孔接触（6e）孔，将电路板与前者分开，并将每个电路板定位成相对于MID部件接触，并将相邻的轨道焊在一起 。 还包括以下独立权利要求：（a）制造多于一个电路板的方法。

公开(公告)号：EP1235233A3

公开(公告)日：2004-01-14

申请号：EP02076768.7

申请日：1994-09-13

Applicant: Tyco Electronics Corporation

Inventor： Fang, Shou-Mean ,  Siden, Denis ,  Thompson, Mark ,  Zhang, Michael

IPC: H01C1/14 ,  H01C7/02 ,  H01C17/28

CPC classification number: H01C17/28 ,  H01C1/1406 ,  H01C7/027 ,  H01C17/06586 ,  H05K1/182 ,  H05K3/0097 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/10469 ,  H05K2201/10666

Abstract: Laminar electrical devices, in particular circuit protection devices, contain two laminar electrodes, with a PTC element between them, and a cross-conductor which passes through the thickness of the device and contacts one only of the two electrodes. This permits connection to both electrodes from the same side of the device. It also makes it possible to carry out the steps for preparing such devices on an assembly which corresponds to a number of individual devices, with division of the assembly as the final step.

公开(公告)号：EP1020908A4

公开(公告)日：2003-08-20

申请号：EP98935341

申请日：1998-08-04

Applicant: TDK CORP

Inventor： GOTOH MASASHI ,  KANAZAWA JITSUO ,  YAMAMOTO SHUICHIRO

IPC: H03H9/145 ,  H01L23/10 ,  H01L23/498 ,  H03H9/05 ,  H03H9/10 ,  H03H9/25 ,  H05K3/00 ,  H05K3/24 ,  H05K3/28 ,  H05K3/34 ,  H05K3/40 ,  H05K3/42 ,  H01L23/12 ,  H03H9/02 ,  H05K1/11

CPC classification number: H05K3/403 ,  H01L23/10 ,  H01L23/49805 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16195 ,  H01L2924/3025 ,  H03H9/1071 ,  H05K3/0052 ,  H05K3/244 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/42 ,  H05K2201/09181 ,  H05K2201/10727 ,  H05K2203/0723 ,  H01L2224/0401

Abstract: Resin-sealed surface mounting type electronic parts which are formed in such a way that an electronic part element (5) is mounted on a resin-made wiring board (1) and a sealed area having a cavity housing the element (5) is formed by bonding a lid member to the board (1) so as to cover the element (5), and then side-face electrodes (21) are formed in through conductive grooves provided inside the bonding surface of the cap member on the board (1). Plated layers in the through conductive grooves have conductors (10 and 11) on the upper and lower surfaces of the board (1) each constituted of two or more kinds of metallic layers containing a plated gold layer (13) formed as the uppermost layer and a plated copper layer (12) and connected to the peripheral edges of the conductive grooves. On the upper conductor (10), however, only the plated copper layer (12) is formed and the other plated layers including the gold layer (13) are not formed on the conductor (10) so as to improve the reliability of the adhesion between the board (1) and cap member. Therefore, the reliability of the adhesion between the board (1) and the cap member for forming the sealed area having a cavity housing the element (5) is improved and the reliability of the airtight sealing of the element (5) is improved.

Abstract translation: 电子元件5安装在树脂布线基板1上，盖构件1以布线基板1的方式接合以覆盖电子元件5，从而构成电子元件5容纳的封装区域， 其内部具有空腔，侧电极21由设置在所述布线基板上的盖构件接合面中的导电贯通槽形成。 所述导电通槽内的镀层由至少两层金属层构成，所述金属层包括作为最上层的Au镀层13和Cu镀层12，并且具有与所述导电通槽的周向周边连接的导体10和11 所述布线基板1的上表面和下表面，同时在导体10上形成单独的Cu镀层12，并且在上表面上不形成包括Au镀层13的其它镀层，以提高接合的可靠性。 提高构成围绕电子元件的封装区域并且具有空腔的树脂布线基板和盖构件的粘合的可靠性，并且提高了气密密封的可靠性。