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    IGBT device with buried emitter regions
    353.
    发明公开
    IGBT device with buried emitter regions 有权
    IGBT-Vorrichtung mit versenkten Emitterregionen

    公开(公告)号：EP2455972A1

    公开(公告)日：2012-05-23

    申请号：EP11189781.5

    申请日：2011-11-18

    Applicant: STMicroelectronics Srl

    Inventor： Patti, Davide Giuseppe

    IPC: H01L29/08 ,  H01L29/739

    CPC classification number: H01L29/7395 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/66333

    Abstract: An IGBT device (200) is proposed. The IGBT device is integrated in a chip of semiconductor material including a substrate (205) of a first type of conductivity, an active layer (115,120) of a second type of conductivity formed on an inner surface (210) of the substrate, a body region (125) of the first type of conductivity extending within the active layer from a front surface (130) thereof opposite the inner surface, a source region (135) of the second type of conductivity extending within the body region from the front surface, a channel region (140) being defined within the body region between the source region and the active layer, a gate element (145) insulated from the front surface extending over the channel region, a collector terminal (C) contacting the substrate on a rear surface (255) thereof opposite the inner surface, an emitter terminal (E) contacting the source region and the body region on the front surface, and a gate terminal (G) contacting the gate element. In the solution according to an embodiment of the invention, the IGBT device includes at least one buried emitter region (260) of the first type of conductivity with a concentration of impurities higher than a concentration of impurities of the substrate being formed in a corresponding portion of the substrate, a further portion of the substrate interposed between the at least one buried emitter region and the collector terminal defining an emitter resistor (Re).

    Abstract translation: 提出了IGBT器件（200）。 IGBT器件集成在半导体材料芯片中，该芯片包括第一导电类型的衬底（205），形成在衬底的内表面（210）上的第二导电类型的有源层（115,120），主体 所述第一类型的导电性区域（125）从所述有源层的与所述内表面相对的前表面（130）延伸，所述第二类型导电体的源极区域（135）从所述前表面延伸到所述体区内， 在所述源极区域和所述有源层之间的所述主体区域中限定的沟道区域（140），与所述沟道区域上方延伸的所述前表面绝缘的栅极元件（145），与所述源极区域和所述有源层之间的所述衬底接触的集电极端子 表面（255）与内表面相对，与源极区域和前表面上的主体区域接触的发射极端子（E）和与栅极元件接触的栅极端子（G）。 在根据本发明的实施例的解决方案中，IGBT器件包括至少一个第一导电类型的掩埋发射极区域（260），其杂质浓度高于在相应部分中形成的衬底的杂质浓度 插入在至少一个掩埋发射极区域和限定发射极电阻器（Re）的集电极端子之间的衬底的另一部分。

    CIRCUIT FOR THE PARALLEL SUPPLYING OF POWER DURING TESTING OF A PLURALITY OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR WAFER
    356.
    发明授权
    CIRCUIT FOR THE PARALLEL SUPPLYING OF POWER DURING TESTING OF A PLURALITY OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR WAFER 有权
    测试几个在半导体晶片集成电子安排。在电路与电源并联供电

    公开(公告)号：EP2324499B1

    公开(公告)日：2012-01-18

    申请号：EP09777658.7

    申请日：2009-08-05

    Applicant: STMicroelectronics Srl

    Inventor： PAGANI, Alberto

    IPC: H01L23/58 ,  G01R31/28

    CPC classification number: H01L22/32 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention relates to a circuit architecture for the parallel supplying of power during an electric or electromagnetic testing, such as EMWS or EWS or WLBI testing, of a plurality of electronic devices (2) each integrated on a same semiconductor wafer (1) wherein the electronic devices (1) are neatly provided on the semiconductor wafer (1) through integration techniques and have edges (5) bounded by separation scribe lines (7). Advantageously according to the invention, the circuit architecture comprises: - at least one conductive grid (4), interconnecting at least one group of the electronic devices (2) and having a portion being external (14) to the devices of the group and a portion being internal (13) to the devices of the group; the external portion (14) of the conductive grid (4) being extended also along the separation scribe lines (7); the internal portion (13) being extended within at least a part of the devices of the group; interconnection pads (6) between the external portion (14) and the internal portion (13) of the conductive grid (4) being provided on at least a part of the devices of the group, the interconnection pads (6) forming, along with the internal and external portions, power supply lines which are common to different electronic devices (2) of the group.

    System for performing the test of digital circuits
    360.
    发明公开
    System for performing the test of digital circuits 有权
    系统zurdurchfürungeinerPrüfungvon digitalen Schaltkreisen

    公开(公告)号：EP2381265A1

    公开(公告)日：2011-10-26

    申请号：EP11159524.5

    申请日：2011-03-24

    Applicant: STMicroelectronics Srl

    Inventor： Casarsa, Marco

    IPC: G01R31/317

    CPC classification number: G01R31/31724 ,  G01R31/31701 ,  G01R31/318555

    Abstract: It is described a system (1) for performing the test of a digital circuit (2). The system comprises a controller (3) configured for executing the test of the digital circuit, comprises a memory (14) configured for storing a status value of the digital circuit, comprises a state machine (6) configured for controlling, before the execution of the test, the storage into the memory of the status value of the digital circuit and configured for controlling, after the execution of the test, the restore into the digital circuit of the status value stored into the memory.

    Abstract translation: 描述了用于执行数字电路（2）的测试的系统（1）。 该系统包括被配置为执行数字电路的测试的控制器（3），包括被配置为存储数字电路的状态值的存储器（14），包括状态机（6），其被配置为在执行 测试中，存储到存储器中的数字电路的状态值并配置为进行控制，执行测试后，将数字电路的状态值还原存储到存储器中。

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