公开(公告)号：EP4174954A1

公开(公告)日：2023-05-03

申请号：EP22204221.0

申请日：2022-10-27

Applicant: STMicroelectronics Pte Ltd.

Inventor： YONG, Yean Ching ,  JIN, Jianhua ,  YAP, Weiyang ,  NGWAN, Voon Cheng

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02 ,  H01L21/336

Abstract: A semiconductor substrate includes: a base substrate layer doped with a first type dopant; a first epitaxial layer on the base substrate layer that has a first thickness and is doped with the first type dopant to provide a first resistivity; a second epitaxial layer on the first epitaxial layer that has a second thickness and is doped with the first type dopant to provide a second resistivity (less than the third resistivity); and a third epitaxial layer on the second epitaxial layer that has a third thickness and is doped with the first type dopant to provide a third resistivity (less than the second resistivity). An oxide field trench transistor includes a trench with insulated polygate and polysource regions extending into the semiconductor substrate and passing through the first doped region, the second doped region, the third epitaxial layer and partially into the second epitaxial layer.

公开(公告)号：EP4102545A1

公开(公告)日：2022-12-14

申请号：EP22305770.4

申请日：2022-05-24

Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics (Tours) SAS

Inventor： LEE, Shin Phay ,  NGWAN, Voon Cheng ,  LANOIS, Frederic ,  TAHIR, Fadhillawati ,  ADNAN, Ditto

IPC: H01L21/329 ,  H01L29/861 ,  H01L29/40

Abstract: A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate/field plate conductor of a field effect rectifier diode.

公开(公告)号：EP2423948A3

公开(公告)日：2012-08-29

申请号：EP11178590.3

申请日：2011-08-24

Applicant: STMicroelectronics Pte Ltd.

Inventor： Ng, Hui Chong Vince ,  Le Neel, Olivier ,  Leung, Calvin

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L23/5228 ,  H01L21/76834 ,  H01L21/76852 ,  H01L28/20 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to an integrated circuit (100) having a substrate (108) and a first and a second interconnect structure (104a,b) over the substrate. Each interconnect structure has a first conductive layer (106) over the substrate and a second conductive layer (124) over the first conductive layer. The integrated circuit also includes a thin film resistor (102) over a portion of the substrate between the first and the second interconnect structure that electrically connects the first conductive layers of the first and second interconnect structures.

公开(公告)号：EP2423948A2

公开(公告)日：2012-02-29

申请号：EP11178590.3

申请日：2011-08-24

Applicant: STMicroelectronics Pte Ltd.

Inventor： Ng, Hui Chong Vince ,  Le Neel, Olivier ,  Leung, Calvin

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/64

CPC classification number: H01L23/5228 ,  H01L21/76834 ,  H01L21/76852 ,  H01L28/20 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to an integrated circuit (100) having a substrate (108) and a first and a second interconnect structure (104a,b) over the substrate. Each interconnect structure has a first conductive layer (106) over the substrate and a second conductive layer (124) over the first conductive layer. The integrated circuit also includes a thin film resistor (102) over a portion of the substrate between the first and the second interconnect structure that electrically connects the first conductive layers of the first and second interconnect structures.

Abstract translation: 本发明涉及在具有基板（108）和第一和第二互连结构（104A，b）在基板的集成电路（100）。 每一个互连结构具有超过基板和在所述第一导电层的第二导电层（124）的第一导电层（106）。 因此，该集成电路包括一个薄膜电阻器（102）在第一和没有导电连接第一和第二互连结构的第一层的第二互连结构之间的衬底的一部分。

公开(公告)号：EP0822651B1

公开(公告)日：2007-04-25

申请号：EP97410083.6

申请日：1997-07-29

Applicant: STMicroelectronics Pte Ltd.

Inventor： Sakti, Rana ,  Chow, Keng-Kwok

IPC: H02P6/18

CPC classification number: H02P6/182

公开(公告)号：EP1498756A1

公开(公告)日：2005-01-19

申请号：EP03291781.7

申请日：2003-07-17

Applicant: STMicroelectronics S.A. ,  STMicroelectronics S.r.l. ,  STMicroelectronics Pte Ltd.

Inventor： Magni, Pierangelo ,  Brechignac, Remi ,  Kho, Chek Lim ,  Loo, Kum Weng

IPC: G02B7/02 ,  H04N5/225

CPC classification number: G02B13/001 ,  G02B7/02 ,  G02B27/62 ,  H01L2224/48227 ,  H04N5/2254

Abstract: On décrit une méthode pour fixer une lentille (8) d'un groupe (11) optique par rapport à un capteur optique (4) dans un dispositif de prise d'images comprenant les phases de:

loger le capteur optique (1) dans un boîtier (2),
fixer un support (12) inférieur du groupe (11) optique au boîtier (1);
aligner un support (13) supérieur du groupe (11) optique, où la lentille (8) est logée, au capteur optique (1) de façon à aligner un point de focalisation de la lentille (8) par rapport au capteur optique (1),
souder le support (13) supérieur au support (12) inférieur.

Avantageusement selon l'invention, la méthode prévoit que la phase de soudure est effectuée par ultrasons.

Abstract translation: 该方法包括将光学传感器（1）容纳在壳体（2）中，并将光学单元（11）的下部支撑件（12）固定到壳体上。 光学单元具有上部支撑件，其中容纳透镜（8），与传感器对准，以使透镜的焦点相对于传感器（1）对准。 光学单元的上支撑件通过能量束与下支撑件焊接。 成像设备包括独立权利要求。

公开(公告)号：EP1125235A1

公开(公告)日：2001-08-22

申请号：EP98951905.3

申请日：1998-10-26

Applicant: STMicroelectronics Pte Ltd.

Inventor： ABSAR, Mohammed, Javed ,  GEORGE, Sapna ,  ALVAREZ-TINOCO, Antonio, Mario

IPC: G06F19/00

CPC classification number: G10L19/0212 ,  G10L19/16

Abstract: AC-3 is a high quality audio compression format widely used in feature films and, more recently, on Digital Versatile Disks (DVD). For consumer applications the algorithm is usually coded into the firmware of a DSP Processor, which due to cost considerations may be capable of only fixed point arithmetic. It is generally assumed that 16-bit processing is incapable of delivering the high fidelity audio, expected from the AC-3 technology. Double precision computation can be utilized on such processors to provide the high quality; but the computational burden of such implementation will be beyond the capacity of the processor to enable real-time operation. Through extensive simulation study of a high quality AC-3 encoder implementation, a multi-precision technique for each processing block is presented whereby the quality of the encoder on a 16-bit processor matches the single precision 24-bit implementation very closely without excessive additional computational complexity.

公开(公告)号：EP4362071A2

公开(公告)日：2024-05-01

申请号：EP23206096.2

申请日：2023-10-26

Applicant: STMicroelectronics Pte Ltd.

Inventor： GANI, David

IPC: H01L21/60 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L24/96 ,  H01L23/5389 ,  H01L23/3128 ,  H01L21/561 ,  H01L21/568

Abstract: The present disclosure is directed to at least one semiconductor package including a die (204) within an encapsulant (202) having a first sidewall, an adhesive layer (222) on the encapsulant and having a second sidewall coplanar with the first sidewall of the encapsulant, and an insulating layer (226) on the adhesive layer having a third sidewall coplanar with the first sidewall and the second sidewall. A method of manufacturing the at least one semiconductor package includes forming an insulating layer on a temporary adhesion layer of a carrier, forming an adhesive layer on the insulating layer, and forming a plurality of openings through the adhesive layer and the insulating layer. The plurality of openings through the adhesive layer and the insulating layer may be formed by exposing the adhesive layer and the insulating layer to a laser.

公开(公告)号：EP4227992A2

公开(公告)日：2023-08-16

申请号：EP23151738.4

申请日：2023-01-16

Applicant: STMicroelectronics Pte Ltd.

Inventor： CHEN, Yong ,  GANI, David

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/16

Abstract: A semiconductor package includes a die and a first lamination layer on the die with openings through the first lamination layer. A redistribution layer is on the first lamination layer and extends through the openings to the die. A plurality of conductive extensions are on the redistribution layer with each stud including a first surface on the redistribution layer, a second surface opposite to the first surface, and a sidewall between the first surface and the second surface. A second lamination layer is on the redistribution layer and the first lamination layer with the die encapsulated in molding compound. The second lamination layer is removed around the conductive extensions to expose the second surface and at least a portion of the sidewall of each stud to improve solder bond strength when mounting the package to a circuit board.

公开(公告)号：EP4084587A1

公开(公告)日：2022-11-02

申请号：EP22169053.0

申请日：2022-04-20

Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics S.r.l.

Inventor： TIZIANI, Roberto ,  HERARD, Laurent

IPC: H05K1/11 ,  H05K3/34 ,  H05K7/20

Abstract: A method of manufacturing electronic devices comprises providing at least one substrate (12) having electrically-conductive tracks (13) patterned thereon. The method further comprises arranging on the at least one substrate (12) at least one semiconductor chip, and electrically coupling the at least one semiconductor chip to selected ones of the electrically-conductive tracks (13). The method further comprises providing, at selected locations on the electrically-conductive tracks (13), containment structures (80) having respective perimeter walls (74, 76) which define respective cavities configured to accommodate a base portion of respective pin holders (16), and soldering the respective pin holders (16) within the cavities defined by the containment structures (80) on the electrically-conductive tracks (13).