公开(公告)号：EP4084587A1

公开(公告)日：2022-11-02

申请号：EP22169053.0

申请日：2022-04-20

Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics S.r.l.

Inventor： TIZIANI, Roberto ,  HERARD, Laurent

IPC: H05K1/11 ,  H05K3/34 ,  H05K7/20

Abstract: A method of manufacturing electronic devices comprises providing at least one substrate (12) having electrically-conductive tracks (13) patterned thereon. The method further comprises arranging on the at least one substrate (12) at least one semiconductor chip, and electrically coupling the at least one semiconductor chip to selected ones of the electrically-conductive tracks (13). The method further comprises providing, at selected locations on the electrically-conductive tracks (13), containment structures (80) having respective perimeter walls (74, 76) which define respective cavities configured to accommodate a base portion of respective pin holders (16), and soldering the respective pin holders (16) within the cavities defined by the containment structures (80) on the electrically-conductive tracks (13).

公开(公告)号：EP4125125A1

公开(公告)日：2023-02-01

申请号：EP22187456.3

申请日：2022-07-28

Applicant: STMicroelectronics S.r.l.

Inventor： MAZZOLA, Mauro ,  TIZIANI, Roberto

IPC: H01L23/498 ,  H01L23/495

Abstract: A pre-molded leadframe is produced starting from a sculptured, electrically conductive laminar structure (10) having empty spaces therein and having a first thickness (D1) with one or more die pads (10) having a first die pad surface (10A) for mounting semiconductor chips as well as a second die pad surface (10B) opposite the first die pad surface (10A). Insulating pre-mold material (12) is molded onto the laminar structure (10) clamped between a pair of planar clamping surfaces (TPS, BPS) kept at a distance equal to the thickness (D1). The pre-mold material (12) penetrates into the empty spaces and provides a laminar pre-molded substrate (10, 12) having the first thickness (D1) with the first die pad surface (10A) left exposed by the pre-mold material (12). The die pad (10) has a second thickness (D2) between the first die pad surface (10A) and the second die pad surface (10B) that is less than the first thickness D1 so that, when clamped between the clamping surfaces (TPS, BPS) the first die pad surface (10A) abuts against the first clamping surface (TPS) and the second die pad surface (10B) is at a distance from the second clamping surface (BPS). One or more pillar formations (100) are provided protruding from the second die pad surface (10B) of a height equal to the difference between the first thickness (D1) and the second thickness (D2). With the laminar structure (10, 14) clamped between the clamping surfaces (TPS, BPS) the pillar formation(s) abut against the second planar clamping surface (BPS). The die pad (10) is thus effectively clamped between the clamping surfaces (TPS, BPS) countering undesired flashing of the pre-mold material (12) over the first die pad surface (10A) .

公开(公告)号：EP4174936A1

公开(公告)日：2023-05-03

申请号：EP22204361.4

申请日：2022-10-28

Applicant: STMicroelectronics S.r.l. ,  Shenzhen STS Microelectronics Co., Ltd.

Inventor： LIANG, Yi Ming ,  TIZIANI, Roberto ,  LIU, Qian ,  DING, Feng

IPC: H01L23/373 ,  C04B37/00 ,  H01L23/433

Abstract: Embodiments of the present disclosure relate to a semiconductor package, a method of forming the package and an electronic device. For example, the semiconductor package may comprise a first substrate assembly comprising a first surface and a second surface opposite the first surface. The semiconductor package may also comprise one or more chips connected or coupled to the first surface of the first substrate assembly by a first thermally and electrically conductive connecting material. In addition, the semiconductor package further comprises a second substrate assembly comprising a third surface and a fourth surface opposite the third surface, the third surface and the first surface being arranged to face each other, and the third surface being connected to one or more chips by a second thermally and electrically conductive connecting material. At least one of the first surface and the third surface is shaped to have a stepped pattern to match a surface of the one or more chips. Embodiments of the present disclosure may at least simplify the double-sided heat dissipation structure and improve the heat dissipation effect of the chip.

公开(公告)号：EP4027165A1

公开(公告)日：2022-07-13

申请号：EP22305004.8

申请日：2022-01-04

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS ,  STMicroelectronics Application GmbH

Inventor： LETOR, Romeo ,  TIZIANI, Roberto ,  RUSSO, Alfio ,  PAVLIN, Antoine ,  LECCI, Nadia ,  GAERTNER, Manuel

IPC: G01S7/484 ,  H01L23/00

Abstract: An electronic module (10) for generating light pulses, comprising: an electronic card or interposer (2); a LASER-diode (5) lighting module (4); and a LASER-diode driver module (6). The interposer has an edge recess in which the lighting module is completely inserted. The driver module is arranged on top of the interposer and the lighting module. The electrical connections for driving the LASER diodes are obtained without resorting to wire bonding in order to reduce the parasitic inductances.

公开(公告)号：EP4099368A1

公开(公告)日：2022-12-07

申请号：EP22175662.0

申请日：2022-05-26

Applicant: STMicroelectronics S.r.l.

Inventor： TIZIANI, Roberto ,  BELIZZI, Antonio

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/36 ,  H01L23/495

Abstract: A method of manufacturing semiconductor devices (100), such as "die pad up" QFN (Quad-Flat No-lead) packages, comprises arranging a plurality of semiconductor chips (C) on an elongated substrate (10) and providing an insulating encapsulation (12) of the semiconductor chips (C). Electrically conductive formations (14) are plated on the insulating encapsulation (12). This may comprise Laser Direct Structuring, LDS or Direct Copper Interconnect, DCI material. Plating may include forming electrically conductive plating lines, the plating lines comprising first transverse plating lines as well as second plating lines 142 branching out from the first plating lines the towards the electrically conductive formations. A first partial cutting step removes the first plating lines extending transversely thus replacing them with grooves into which insulating material (18) is dispensed to encapsulate the end portions (142a) of the second plating lines (142). A second cutting step (B2) through the elongate substrate (10) having the semiconductor chips (C) arranged thereon and the insulating encapsulation (12) produces singulated semiconductor devices wherein the end portions (142a) of the second plating lines (142) are encapsulated by the insulating material (18).

公开(公告)号：EP4016617A1

公开(公告)日：2022-06-22

申请号：EP21215210.2

申请日：2021-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： MAZZOLA, Mauro ,  TIZIANI, Roberto

IPC: H01L23/498 ,  H01L23/495

Abstract: In a method of manufacturing semiconductor devices, one or more semiconductor chips are arranged at a semiconductor chip mounting area (14) in a first surface of a leadframe (10).
The leadframe comprises a pattern of electrically-conductive formations (12, 14, 14', 14") with one or more sacrificial connection formations (100) extending bridge-like between a pair of electrically-conductive formations (14, 14'). The sacrificial connection formation or formations (100) are formed at one of the first surface and the second surface of the leadframe (10) and have a thickness less than the leadframe thickness between the first surface and the second surface. A filling of electrically-insulating material (16) is molded between the electrically-conductive formations of the leadframe, with electrically-insulating material molded between the connection formation(s) and the other surface of the leadframe (10). The sacrificial connection formation(s) counter deformation and displacement of parts during formation and pre-molding of the leadframe (10).

公开(公告)号：EP3840039A1

公开(公告)日：2021-06-23

申请号：EP20213302.1

申请日：2020-12-11

Applicant: STMicroelectronics S.r.l.

Inventor： DERAI, Michele ,  TIZIANI, Roberto

IPC: H01L23/495

Abstract: A semiconductor device (10) comprises at least one semiconductor die (50) electrically coupled (54) to a set of electrically conductive leads, and package molding material (100) molded over the at least one semiconductor die (50) and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material (100) to provide electrically conductive pads (12, 44). The electrically conductive pads (12, 44) comprise enlarged end portions (44) extending at least partially over the package molding material (100) and configured for coupling to a printed circuit board (30).