公开(公告)号：WO0052824A9

公开(公告)日：2001-11-29

申请号：PCT/US0005483

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： PARK JIM ,  HUANG WEI-JEN ,  NGAI TONY ,  PEDERSON BRUCE A

IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17792

Abstract: A programmable logic device is adapted to predict carry values in long-chain-carry logic configurations. In the most preferred embodiment, which functions in any long-carry-chain logic configuration, each logic region calculates a result for both values of the carry-in signal to that region, and when a carry signal for the group to which the region belongs reaches the region, the correct result in each region, and thece the correct carry-out for that group, are calculated and propagated. The carry-out terminal of one group is arranged to be adjacent to the carry-in terminal of the next group, to enhance carry propagation speed. In another embodiment, each region looks back two regions to predict the carry-in. In two additional embodiments, logic is provided to mathematically calculate the carry values.

Abstract translation: 可编程逻辑器件适用于预测长链进位逻辑配置中的进位值。 在最优选的实施例中，其在任何长承载链逻辑配置中起作用，每个逻辑区域计算对于该区域的进位信号的两个值的结果，以及当该区域所属的组的进位信号 到达区域，每个区域的正确结果，以及该组的正确执行情况都被计算和传播。 一组的进位终端被布置成与下一组的进位终端相邻，以提高进位传播速度。 在另一个实施例中，每个区域回顾两个区域以预测携带。 在两个附加实施例中，提供逻辑以在数学上计算进位值。

公开(公告)号：WO0031652A2

公开(公告)日：2000-06-02

申请号：PCT/US9927485

申请日：1999-11-19

Applicant: ALTERA CORP

Inventor： SMITH STEPHEN J ,  SOUTHGATE TIMOTHY J

IPC: G06F11/00 ,  G06F15/78 ,  G06F17/50

CPC classification number: G06F17/5054

Abstract: A reconfigurable computer system based on programmable logic is provided. A system design language may be used to write applications. The applications may be automatically partitioned into software components and programmable logic resource components. A virtual computer operating system may be provided to schedule and allocate system resources. The virtual computer operating system may include a virtual logic manager that may increase the capabilities of programmable logic resources in the system.

Abstract translation: 提供了一种基于可编程逻辑的可重构计算机系统。 系统设计语言可用于编写应用程序。 应用程序可以自动分为软件组件和可编程逻辑资源组件。 可以提供虚拟计算机操作系统来调度和分配系统资源。 虚拟计算机操作系统可以包括可以增加系统中可编程逻辑资源的能力的虚拟逻辑管理器。

公开(公告)号：WO2013106032A3

公开(公告)日：2013-10-17

申请号：PCT/US2012032602

申请日：2012-04-06

Applicant: ALTERA CORP ,  CHIU GORDON RAYMOND ,  GOH TEIK MING ,  JAZMI MUHAMAD AIDIL ,  ONG YU YING

Inventor： CHIU GORDON RAYMOND ,  GOH TEIK MING ,  JAZMI MUHAMAD AIDIL ,  ONG YU YING

IPC: G06F13/14 ,  G06F12/00

CPC classification number: G06F13/1626

Abstract: Systems and methods for using memory commands are described. The systems include a memory controller. The memory controller receives a plurality of user transactions. The memory controller converts each user transaction into one or more read or write memory commands. The memory controller reorders the memory commands associated with the plurality of user transactions before sending the memory commands to a memory device.

Abstract translation: 描述了使用存储器命令的系统和方法。 这些系统包括一个内存控制器。 存储器控制器接收多个用户事务。 存储器控制器将每个用户事务转换成一个或多个读或写存储器命令。 在将存储器命令发送到存储器设备之前，存储器控制器重新排列与多个用户事务相关联的存储器命令。

公开(公告)号：WO2012018799A3

公开(公告)日：2012-05-24

申请号：PCT/US2011046246

申请日：2011-08-02

Applicant: ALTERA CORP ,  LEE ANDY L ,  WATT JEFFREY T

Inventor： LEE ANDY L ,  WATT JEFFREY T

IPC: H03K19/173 ,  G06F9/06

CPC classification number: H03K19/173 ,  G11C5/005 ,  H01L27/0207 ,  H03K19/1736 ,  H03K19/17784

Abstract: Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.

Abstract translation: 硬化可编程逻辑器件提供有可编程电路。 可编程电路可以是硬连线的，以实现定制逻辑电路。 可以使用通用制造掩模来形成可编程电路，并且可以用于制造硬化的可编程逻辑器件的产品系列，每一个可以实现不同的定制逻辑电路。 可以使用定制制造掩模来硬编程电路来实现特定的定制逻辑电路。 可编程电路可以是硬连线的，使得实现定制逻辑电路的硬化可编程逻辑器件的信号定时特性可以匹配使用配置数据实现相同定制逻辑电路的可编程逻辑器件的信号定时特性。

公开(公告)号：WO2012006553A3

公开(公告)日：2012-04-19

申请号：PCT/US2011043402

申请日：2011-07-08

Applicant: ALTERA CORP ,  KIPPER MICHAEL HOWARD ,  FENDER JOSHUA DAVID ,  AZIZI NAVID ,  GOLDMAN DAVID SAMUEL

Inventor： KIPPER MICHAEL HOWARD ,  FENDER JOSHUA DAVID ,  AZIZI NAVID ,  GOLDMAN DAVID SAMUEL

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5077 ,  G06F2217/82

Abstract: Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value assignments or as a list of possible value assignments. Further, the method includes an operation for determining the minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin. Additionally, other method operations are included for routing paths to the I/O pins to meet the actual switching times and for creating a design for the IC that meets the actual switching times.

Abstract translation: 介绍了利用计算机辅助设计（CAD）工具设计的集成电路（IC）中降低同时开关噪声（SSN）的方法和装置。 在一种方法中，CAD工具接收到IC参数的值分配。 值分配作为值分配的范围输入，或作为可能的值分配列表。 此外，该方法包括用于确定I / O块中的每个输入/输出（I / O）引脚的最小和最大路径延迟的操作，使得满足接收的值分配。 I / O引脚的实际切换时间及时扩展，以降低I / O引脚中的SSN。 切换时间被分散，以使切换时间落在对应的I / O引脚的最小和最大路径延迟之间。 此外，还包括其他方法操作，用于路由到I / O引脚的路径，以满足实际切换时间，并为IC创建满足实际切换时间的设计。

公开(公告)号：WO2011149772A3

公开(公告)日：2012-01-19

申请号：PCT/US2011037309

申请日：2011-05-20

Applicant: ALTERA CORP ,  NGUYEN ANDY

Inventor： NGUYEN ANDY

IPC: H03K19/0175 ,  H03L7/08

CPC classification number: H03K19/0175 ,  G06F1/08 ,  G06F1/10 ,  H03L7/23

Abstract: A first periodic signal generation circuit generates first periodic output signals. A second periodic signal generation circuit generates second periodic output signals. A first multiplexer circuit receives the first and the second periodic output signals. An interface circuit coupled to external pins generates a third periodic output signal based on a periodic signal selected by the first multiplexer circuit. A second multiplexer circuit receives the third periodic output signal at an input. A first periodic feedback signal provided to the first periodic signal generation circuit is based on a signal selected by the second multiplexer circuit. A third multiplexer circuit receives the third periodic output signal at an input. A second periodic feedback signal provided to the second periodic signal generation circuit is based on a signal selected by the third multiplexer circuit.

Abstract translation: 第一周期性信号产生电路产生第一周期性输出信号。 第二周期信号产生电路产生第二周期性输出信号。 第一多路复用器电路接收第一和第二周期性输出信号。 耦合到外部引脚的接口电路基于由第一多路复用器电路选择的周期性信号产生第三周期性输出信号。 第二复用器电路在输入端接收第三周期性输出信号。 提供给第一周期信号产生电路的第一周期性反馈信号基于由第二多路复用器电路选择的信号。 第三多路复用器电路在输入端接收第三周期性输出信号。 提供给第二周期信号产生电路的第二周期性反馈信号基于由第三多路复用器电路选择的信号。

公开(公告)号：WO2011119606A3

公开(公告)日：2011-12-29

申请号：PCT/US2011029427

申请日：2011-03-22

Applicant: ALTERA CORP ,  LANGHAMMER MARTIN

Inventor： LANGHAMMER MARTIN

IPC: G06F7/50 ,  H03K19/173 ,  H03K19/21

CPC classification number: G06F17/10 ,  G06F7/5057 ,  G06F7/506 ,  G06F7/509

Abstract: A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.

Abstract translation: 具有多个查找表的查找表结构被配置为包括四进制加法器。 在具体示例中，包括可分解查找表（LUT）的自适应逻辑模块（ALM）被配置为包括四进制（4-1）加法器。 在一些示例中，仅需要XOR门，AND门，两个单位2-1多路复用器以及支持三进制（3-1）加法器的LUT结构的次要连接性改变以支持4-1加法器。 二进制（2-1）和三进制加法器仍然支持使用原始信号流，因为三进制加法器特征可以容易地多路复用。

公开(公告)号：WO2011156771A2

公开(公告)日：2011-12-15

申请号：PCT/US2011040069

申请日：2011-06-10

Applicant: ALTERA CORP ,  RAVI AJAY K ,  LEWIS DAVID

Inventor： RAVI AJAY K ,  LEWIS DAVID

IPC: H03K5/15 ,  G06F1/10 ,  H03L7/06

CPC classification number: H03K3/017 ,  G06F1/10 ,  H03K5/1565

Abstract: Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output pins. The clock signals may be routed through a clock distribution network to provide local clock signals to pulse generators that generate clock pulses on rising and falling clock edges. The pulse generators may generate clock pulses that are triggered by the rising and falling clock edges with a common pulse width for optimum performance. Duty cycle distortion introduced by the clock network may be minimized for optimum performance. Adaptive duty cycle distortion circuitry may be used to control the pull- up/pull-down drive strengths of the clock buffer so that the high clock phase of the local clock signals is approximately a half clock cycle.

Abstract translation: 提供支持双边沿时钟的集成电路。 集成电路可以包括产生方波时钟信号的锁相环。 时钟信号可以通过输入输出引脚从片外设备提供。 时钟信号可以通过时钟分配网络路由，以向本地时钟信号提供脉冲发生器，以在时钟沿上升沿和下降沿产生时钟脉冲。 脉冲发生器可以产生由具有公共脉冲宽度的上升和下降时钟沿触发的时钟脉冲，以获得最佳性能。 时钟网络引入的占空比失真可能被最小化以获得最佳性能。 可以使用自适应占空比失真电路来控制时钟缓冲器的上拉/下拉驱动强度，使得本地时钟信号的高时钟相位大约为半个时钟周期。

公开(公告)号：WO2011014434A3

公开(公告)日：2011-04-28

申请号：PCT/US2010043137

申请日：2010-07-23

Applicant: ALTERA CORP ,  HATA WILLIAM Y

Inventor： HATA WILLIAM Y

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H01L24/06 ,  H01L22/32 ,  H01L23/3171 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/00014

Abstract: An integrated circuit (IC) that includes a plurality of bond pads disposed on a surface of the IC and a plurality of probe pads disposed on the surface of the IC is provided. Each of the plurality of probe pads is in electrical communication with corresponding bond pads. The plurality of probe pads are linearly configured across the surface. In one embodiment, the probe pads are disposed along a diagonal of the surface of the die defined between opposing vertices of the die surface. In another embodiment, multiple rows of linearly disposed probe pads are provided on the surface. In addition a packaging architecture for an integrated circuit is provided. The architecture includes a printed circuit board and a package substrate disposed on the printed circuit board. A first integrated circuit is disposed on a first surface of the package substrate. The package substrate is capable of supporting a second integrated circuit. The second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate. Each of the plurality of pads is in electrical communication with the printed circuit board without communicating with the first integrated circuit.

Abstract translation: 提供了一种集成电路（IC），其包括设置在IC表面上的多个接合焊盘和设置在IC表面上的多个探针焊盘。 多个探针垫中的每一个都与对应的接合垫电连通。 多个探测垫在表面上线性构造。 在一个实施例中，探针垫沿着在芯片表面的相对顶点之间限定的芯片表面的对角线设置。 在另一个实施例中，在表面上提供多行线性设置的探针垫。 此外还提供了用于集成电路的封装体系结构。 该架构包括印刷电路板和设置在印刷电路板上的封装衬底。 第一集成电路设置在封装衬底的第一表面上。 封装衬底能够支撑第二集成电路。 第二集成电路与设置在封装衬底的第一表面上的多个焊盘电连通。 多个垫中的每一个都与印刷电路板电通信，而不与第一集成电路通信。

公开(公告)号：WO2011038404A2

公开(公告)日：2011-03-31

申请号：PCT/US2010050573

申请日：2010-09-28

Applicant: ALTERA CORP

Inventor： PEDERSON BRUCE ,  CHOKKALINGAM SIVARAMAN

IPC: G06F9/305

CPC classification number: H03K3/0375 ,  H03K3/356121 ,  H03K3/356139

Abstract: A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of physical inputs.

Abstract translation: 亚稳亚稳态存储电路包括至少一个反相电路。 反相电路有一个逻辑输入。 反相电路的逻辑输入被分成一对物理输入。