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公开(公告)号：AU2011200479A1
公开(公告)日：2011-02-24
申请号：AU2011200479
申请日：2011-02-04
Applicant: ATI TECHNOLOGIES INC
Inventor： MOREIN STEVEN , LEFEBVRE LAURENT , GRUBER ANDY , SKENDE ANDI
Abstract: A graphics processor, comprising an arbiter circuit having vertex data provided at a first input and pixel data provided at a second input, wherein arbiter circuit is configured to select to transmit the vertex data at the first input or the pixel data at the second input; and a unified shader coupled to the arbiter circuit, wherein the unified shader is configured to simultaneously perform the vertex operations and the pixel operations on the vertex data and the pixel data by switching between the vertex operations and the pixel operations, and the unified shader comprises: a register block coupled to the arbiter circuit configured to maintain the vertex data and the pixel data in the unified shader, a processor unit coupled to the register block, wherein the processor unit is configured to execute vertex operations and pixel operations, and a sequencer coupled to the processor unit and the register block, wherein the sequencer is operative to cause the processor unit to execute the vertex operations and the pixel operations on the vertex data and the pixel data.
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公开(公告)号：DE60034511T2
公开(公告)日：2008-01-03
申请号：DE60034511
申请日：2000-06-21
Applicant: ATI TECHNOLOGIES INC , ATI INT SRL
Inventor： GRIMWOOD MICHAEL , LIND PAUL ALAN , RAKIB SELIM SHLOMO
Abstract: A method for allowing upstream channels having the same multiplexing type but different symbol rates or the same symbol rates but different multiplexing types to be transmitted on the same frequency band without interfering with each other. In particular, a method for allowing DOCSIS 1.0 TDMA only cable modems to coexist on a digital data delivery distributed system with DOCSIS 1.2 TDMA or SCDMA mode cable modems without the need for modification of the DOCSIS 1.0 cable modems or the need for the DOCSIS 1.0 modems to transmit on a different frequency. The method comprises: using a plurality of upstream channel descriptor messages transmitted from said central modem to said distributed modems to define a plurality of different upstream logical channels sharing the same frequency band, each said logical channel having either a different symbol rate but the same multiplexing type or the same multiplexing type but a different symbol rate, said upstream channel descriptor messages assigning each of said distributed modems to logical channels appropriate to the symbol rate and modulation type of said distributed modem; and, scheduling transmission bursts on each said logical channel by transmitting a bandwidth award and scheduling message for each logical channel each of which defines and controls which distributed modems on the logical channel to which the bandwidth award and scheduling message can transmit and when they can transmit, said bandwidth award and scheduling messages being coordinated by said central modem so that there is never any overlap in time between transmission bursts on different logical channels sharing the same frequency band.
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公开(公告)号：CA2585860A1
公开(公告)日：2006-06-02
申请号：CA2585860
申请日：2004-11-19
Applicant: ATI TECHNOLOGIES INC
Inventor： MOREIN STEVEN , LEFEBVRE LAURENT , GRUBER ANDY , SKENDE ANDI
Abstract: A graphics processor, comprising an arbiter circuit having vertex data provided at a first input and pixel data provided at a second input, wherein arbiter circuit is configured to select to transmit the vertex data at the first input or the pixel data at the second input; and a unified shader coupled to the arbiter circuit, wherein the unified shader is configured to simultaneously perform the vertex operations and the pixel operations on the vertex data and the pixel data by switching between the vertex operations and the pixel operations, and the unified shader comprises: a register block coupled to the arbiter circuit configured to maintain the vertex data and the pixel data in the unified shader, a processor unit coupled to the register block, wherein the processor unit is configured to execute vertex operations and pixel operations, and a sequencer coupled to the processor unit and the register block, wherein the sequencer is operative to cause the processor unit to execute the vertex operations and the pixel operations on the vertex data and the pixel data.
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公开(公告)号：CA2122079C
公开(公告)日：1999-02-23
申请号：CA2122079
申请日：1994-04-25
Applicant: ATI TECHNOLOGIES INC
Inventor： LI RAYMOND M L , QUAN HENRY
IPC: G06F13/38
Abstract: The present invention relates to a universal peripheral interface comprised of control logic circuits for a plurality of peripherals carrying different signals on different pins of respective peripheral connectors, a single interface connector for mating with any of the peripheral connectors, a first multiplexer for interfacing any of the control logic circuits with the single interface connector and for switching particular lines of each of the control logic circuits carrying particular signals to particular pins of the single connector, and apparatus for controlling the multiplexer to map the lines to the particular pins of the single connector.
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公开(公告)号：CA2105107C
公开(公告)日：1999-01-19
申请号：CA2105107
申请日：1993-08-30
Applicant: ATI TECHNOLOGIES INC
Inventor： SETO JIM M N , COLBECK ROGER P , CHAU RAYMOND , LEUNG SIMON C F
Abstract: A voltage to current converter is formed of a first current steering mirror which includes first binary weighted current mirror transistors and receives an input voltage signal and converts it to an output current. The converter also is formed of a second current mirror which generates a selectable output current, the second current mirror being formed of second binary weighted current mirror transistors. The output currents of the first current steering mirror and second current mirror are added and the sum is provided to the control input of a current controlled oscillator which can be used in a phase locked loop.
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Patent Agency Ranking
公开(公告)号：CA2134847A1
公开(公告)日：1996-02-11
申请号：CA2134847
申请日：1994-11-01
Applicant: ATI TECHNOLOGIES INC
Inventor： LUM SANFORD S , KIELBASINSKI JERZY , HARTOG ADRIAN
IPC: G06F15/66
Abstract: A method of operating a graphics accelerator draw engine containing registers comprised of saving a state of the registers (contexts) of the draw engine in a predetermined memory area of a memory, loading the draw engine from the memory with the context using a single processor write command, and executing an operation of the draw engine.
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公开(公告)号：CA2102936A1
公开(公告)日：1995-03-31
申请号：CA2102936
申请日：1993-11-12
Applicant: ATI TECHNOLOGIES INC
Inventor： LEONE PASQUALE
Abstract: The present invention relates to a method of aligning and blending input digital samples, comprised of delaying the input samples by a clock pulse, to provide delayed data samples, subtracting a smaller fractional part from a larger fractional part of either an input sample number and a requested sample number to provide a sample difference number first factor, subtracting the sample difference number from 1 to provide a second factor, multiplying either of the input samples or the delayed samples by the first factor to provide a first result, multiplying the other of the input samples or the delayed samples by the second factor to provide a second result, and adding the results to provide output samples.
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公开(公告)号：CA2102942A1
公开(公告)日：1995-03-11
申请号：CA2102942
申请日：1993-11-12
Applicant: ATI TECHNOLOGIES INC
Inventor： LUM SANFORD S , CHEN KEPING
Abstract: The present invention relates to a method of converting signal components of one of a first input three component color model signal and a second input three component color model signal to either one of the first or second three component color model comprised of matrix multiplying input signal components with an array of predetermined transformation parameters to form a multiplied set, vector adding the multiplied set with a predetermined group of offset vectors, whereby signal components of the output signal are produced.
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公开(公告)号：CA2105107A1
公开(公告)日：1994-12-24
申请号：CA2105107
申请日：1993-08-30
Applicant: ATI TECHNOLOGIES INC
Inventor： SETO JIM M N , COLBECK ROGER P , CHAU RAYMOND , LEUNG SIMON C F
Abstract: A voltage to current converter is formed of a first current steering mirror which includes first binary weighted current mirror transistors and receives an input voltage signal and converts it to an output current. The converter also is formed of a second current mirror which generates a selectable output current, the second current mirror being formed of second binary weighted current mirror transistors. The output currents of the first current steering mirror and second current mirror are added and the sum is provided to the control input of a current controlled oscillator which can be used in a phase locked loop.
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公开(公告)号：CA2585860C
公开(公告)日：2014-10-28
申请号：CA2585860
申请日：2004-11-19
Applicant: ATI TECHNOLOGIES INC
Inventor： MOREIN STEVEN , LEFEBVRE LAURENT , GRUBER ANDY , SKENDE ANDI
Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
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