公开(公告)号：JPH1167971A

公开(公告)日：1999-03-09

申请号：JP14974098

申请日：1998-05-29

Applicant: ST MICROELECTRON INC

Inventor： CHAN TSIU C ,  LAWRENCE P ENG

IPC: H05K1/18 ,  H01L23/12 ,  H01L23/14

Abstract: PROBLEM TO BE SOLVED: To provide a high-level integration for forming the entire system, by forming an interconnection layer on a board and fixing integrated circuits to the interconnection layer. SOLUTION: An integrated circuit package comprises a board 12, and integrated circuits 14, 16, 18, 20, 22 which are fixed to the board 12 and comprise integrated circuit outer connections, contacts or bond pads 24, 26, 28, 30, 23. An Si wafer or board 12 comprises board contacts or bond pads 34, 36, 38, 40, 42. Interconnections or bonding wires 44 are formed between the integrated circuit 24, 26, 28, 30, 32 and bond pads 34, 36, 38, 40, 42 to form electric connections from the integrated circuits 14, 16, 18, 20, 22 to the board 12, thereby expanding the capability for integrating many chips or integrated circuits.

公开(公告)号：JPH1155984A

公开(公告)日：1999-02-26

申请号：JP15083998

申请日：1998-06-01

Applicant: ST MICROELECTRON INC

Inventor： MENEGOLI PAOLO

IPC: H02P6/06 ,  G11B19/20 ,  H02P6/10

Abstract: PROBLEM TO BE SOLVED: To reduce generation of undesired noise, by supplying a control current based on a control signal representing a motor speed, and supplying a control voltage based on the control current to a control terminal of a driving transistor via a transmitting circuit. SOLUTION: The gate of a transistor M2 is connected to an altspeed control signal representing a rotor speed. If the rotor speed is lower than a threshold speed, the control signal is low, and the transistor M2 is turned OFF. Meanwhile, when the rotor speed exceeds the threshold speed, the control signal becomes high, and the transistor M2 is turned ON. And, current via the transistors Q2, M2 starts to flow. Thus, a control circuit 15 controls a slew rate of the low side driving transistor in response to the rotor speed. And, the slew rare is reduced during a period of high current recalculation via a coil. Thus, generation of sound noise due to rapid ON and OFF of the switch is prevented.

公开(公告)号：JPH1126603A

公开(公告)日：1999-01-29

申请号：JP12624298

申请日：1998-05-08

Applicant: ST MICROELECTRON INC

Inventor： MENEGOLI PAOLO

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H02H7/122 ,  H02M1/08

Abstract: PROBLEM TO BE SOLVED: To avoid the parasitic effect such as below-ground effect of a junction separation type IC by forcedly turning on a specified driver transistor forming a part of a parasitic transistor. SOLUTION: An IC 10 comprises a sequence control circuit 16 having a three-phase full-wave bridge circuit 14 for driving a load 12 and elements for commutating the operation of elements of a bridge circuit for applying an accurately timed current generated by a feed Vcc to segments of the load 12. The circuit 16 has various control loops for operation of the IC 10 as a brushless motor driver circuit and often so-called peripheral circuits. The circuit 14 has power transistor drivers 18A-18C, 19A-19C for comparing with a lower current of the circuit 16 to flow, e.g. a considerable current of at least several amperes, thereby avoiding the adverse parasitic effect of an IC having power devices.

公开(公告)号：JPH10254699A

公开(公告)日：1998-09-25

申请号：JP35647097

申请日：1997-12-25

Applicant: ST MICROELECTRON INC

Inventor： ISAMAN DAVID L

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/318 ,  G06F9/34 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To decrease the number of needed clocks and to facilitate floating point exchanging operation by allowing a physical register to hold the same contents for respective exchange instructions. SOLUTION: An instruction server 106 retrieves one or more insurrections from an instruction cache 104. Four parcels are stored in parcel registers 108A to 108D. Each parcel register sends the parcels to corresponding decoders 110A to 110D, which decode the parcels, determine whether or not the parcels have a floating point exchange instruction, and further determine their operand registers. Then the decoded instructions are sent to corresponding logic units 112A to 112D. The logic units 112A to 112D further receive top-of-stack information and also receive current or existing FXCH maps each time a floating point exchange instruction is received.

公开(公告)号：JP2014072525A

公开(公告)日：2014-04-21

申请号：JP2013197498

申请日：2013-09-24

Applicant: St Microelectron Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics, Inc. ,  Internatl Business Machines Corp ,  インターナショナル ビジネス マシーンズ コーポレイションInternational Business Machines Corporation

Inventor： ZHANG JOHN H ,  CLEVENGER LAWRENCE A ,  CARL RADENS ,  YIHENG XU

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76834 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a system and method of novel encapsulated multi metal branch foot structures for an advanced back end of the line.SOLUTION: A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between the metal tracks in the intermetal dielectric layers.

Abstract translation: 要解决的问题：提供一种用于线路后端的新型封装的多金属分支脚结构的系统和方法。解决方案：在集成电路模具中堆叠的多个金属间电介质层中形成多个金属轨道 。 在金属轨道周围形成薄的保护电介质层。 保护性介电层用作硬掩模以限定金属间介电层中的金属轨道之间的接触通孔。

公开(公告)号：JP2014060389A

公开(公告)日：2014-04-03

申请号：JP2013171445

申请日：2013-08-21

Applicant: St Microelectron Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics, Inc.

Inventor： ZHANG JOHN H

IPC: H01L21/304

CPC classification number: B24B7/228 ,  B24B37/005 ,  B24B49/04 ,  B24B49/105

Abstract: PROBLEM TO BE SOLVED: To provide an improved semiconductor processing method and device.SOLUTION: The method may include measuring at least one property of a semiconductor wafer and determining a procedure for processing the semiconductor wafer on the basis of the at least one property. The semiconductor wafer may be processed with a plurality of chemical mechanical polishing (CMP) modules on the basis of the determined procedure, and the procedure includes a value of at least one parameter for use by each of the plurality of CMP modules. The measurements may be made in situ or by an in-line measurement device. The procedure and various parameters associated with the procedure may be determined by a controller of the semiconductor processing device.

Abstract translation: 要解决的问题：提供一种改进的半导体处理方法和装置。解决方案：该方法可以包括测量半导体晶片的至少一个性质并且基于该至少一个特性确定用于处理半导体晶片的过程。 可以基于确定的过程用多个化学机械抛光（CMP）模块来处理半导体晶片，并且该过程包括用于多个CMP模块中的每一个的至少一个参数的值。 测量可以在原位或通过在线测量装置进行。 与该过程相关的过程和各种参数可以由半导体处理装置的控制器确定。

公开(公告)号：JP2010160895A

公开(公告)日：2010-07-22

申请号：JP2010029868

申请日：2010-02-15

Applicant: St Microelectron Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics,Inc.

Inventor： SLEZAK YARON ,  ZIKLIK ARYE ,  TRINH CUONG QUOC

IPC: G11C16/06 ,  G11C29/12 ,  G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318533

Abstract: PROBLEM TO BE SOLVED: To provide a memory chip of which the general purpose port can be used as a JTAG port.
SOLUTION: The memory chip which uses a multi-pin port as the JTAG port, is provided with a JTAG controller, at least one internal block, and composition unit, and one four-pins of the multi-pin port of the chip is selectively composed by the composition unit, and the JTAG data are transmitted to the JTAG controller or non-JTAG data are transmitted to at least one internal block. The composition unit can permanently or changeably composed in general. For example, the composition unit which can be changed, is a volatile memory (VM) composition unit or it can be product term output of programmable logic device (PLD).
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供通用端口可以用作JTAG端口的存储器芯片。

解决方案：使用多针端口作为JTAG端口的存储器芯片设置有JTAG控制器，至少一个内部块和组合单元，以及多针端口的一个四针 芯片由组合单元选择性地组成，并且JTAG数据被发送到JTAG控制器，或者非JTAG数据被发送到至少一个内部块。 组合单元可以永久地或可变地组成。 例如，可以改变的组合单元是易失性存储器（VM）组成单元，或者它可以是可编程逻辑器件（PLD）的产品术语输出。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009223909A

公开(公告)日：2009-10-01

申请号：JP2009134672

申请日：2009-06-04

Applicant: St Microelectron Inc ,  エスティーマイクロエレクトロニクス,インコーポレイテッドSTMicroelectronics,Inc.

Inventor： SLEZAK YARON ,  CEDAR YORAM ,  WIENNER ILAN

IPC: G06F13/14 ,  G06F13/42 ,  G06F9/24

CPC classification number: G06F9/24

Abstract: PROBLEM TO BE SOLVED: To provide a new apparatus and method for input and output control reducing the time required for the input and output process of an on-chip memory unit via a JTAG port.
SOLUTION: A signal indicating whether a memory unit is in a state where it is capable of the input and output process (ready state) or in a state where it is not capable of the input and output process (busy state) is received. When a display enters the ready state, instructions for performing the next input and output process of the memory unit (read, write data of such as programs, delete, verify, etc.) are issued so as to control the input and output process of the on-chip memory unit.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于输入和输出控制的新装置和方法，其通过JTAG端口减少片上存储器单元的输入和输出处理所需的时间。 解决方案：指示存储器单元是否处于能够进行输入和输出处理（就绪状态）或不能进行输入和输出处理（繁忙状态）的状态的信号是 收到了 当显示器进入就绪状态时，发出用于执行存储器单元的下一个输入和输出处理（读取，写入数据，例如程序，删除，验证等）的指令，以控制输入和输出处理 片上存储单元。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JPH11122338A

公开(公告)日：1999-04-30

申请号：JP21804298

申请日：1998-07-31

Applicant: ST MICROELECTRON INC

Inventor： MA HERMAN

IPC: H03K19/177 ,  H04M1/26 ,  H04M1/27

Abstract: PROBLEM TO BE SOLVED: To provide a dialer provided with an address system. SOLUTION: An option selection circuit of the dialer includes an internal address generator 20 that generates an address pattern outputted from a multiplexer 14 to an I/O pin 10 in the set-up mode. The pin 10 is wired selectively to an address input pin via an interface circuit 24 and an address is given to a decoder 28. The decoder 28 decodes the selected address and the decoded address is given to a PLA 30. Thus, various functions produced by a function generator 12 are selected for the operation of the usual dialer mode. The interface circuit 24 includes hardware wiring connections.

公开(公告)号：JPH11102229A

公开(公告)日：1999-04-13

申请号：JP15315798

申请日：1998-06-02

Applicant: ST MICROELECTRON INC

Inventor： CHAN TSUI CHIU ,  SAGARWALA PERVEZ H

IPC: H01L21/8234 ,  G05F3/20 ,  G05F3/24 ,  G11C5/14 ,  H01L27/088 ,  H03F1/30

Abstract: PROBLEM TO BE SOLVED: To reduce the supply voltage and standby current of the integrated circuit by generating the absolute value of the effective threshold voltage of only a selected MOSFET less than the absolute value of an initial threshold voltage and inhibiting a high standby current at this time. SOLUTION: Only the well of one MOSFET selected between MOSFETs 12 and 13 of the integrated circuit 10 is selectively biased. The MOSFETs 12 and 13 have initial threshold voltages. Selective bias operation generates the absolute value of the effective threshold voltage of only the selected MOSFET which is less than the absolute value of the initial threshold voltage and the high standby current to the integrated circuit 10 is inhibited. Therefore, the MOSFETs 12 and 13 can be operated with supply voltages lower than about 1 V.