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    DIFFERENTIAL AMPLIFIER
    32.
    发明专利
    DIFFERENTIAL AMPLIFIER 未知

    公开(公告)号：FR3009147A1

    公开(公告)日：2015-01-30

    申请号：FR1357283

    申请日：2013-07-24

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS PVT LTD

    Inventor： LE TUAL STEPHANE ,  SINGH PRATAP NARAYAN

    IPC: H03F3/45 ,  H03F1/02 ,  H03F1/26 ,  H03F1/34 ,  H03F1/42

    Abstract: L'invention concerne un amplificateur différentiel comportant : une première branche (201) comprenant un premier transistor (202) et un premier composant (204) ; une deuxième branche (211) comprenant un deuxième transistor (212) et un deuxième composant (214) ; dans lequel le premier transistor comprend un noeud de commande adapté à recevoir un premier signal d'entrée différentiel (IN+), et un autre noeud de commande (224) adapté à recevoir un premier signal de contreréaction (VBG+) basé sur au moins un deuxième signal de sortie (OUT+) provenant de la deuxième branche, et le deuxième transistor comprend un noeud de commande adapté à recevoir un deuxième signal d'entrée différentiel (IN-), et un autre noeud de commande (226) adapté à recevoir un deuxième signal de contre-réaction (VBG_) basé sur au moins un premier signal de sortie (OUT-) provenant de la première branche.

    Flexible communications
    37.
    发明专利
    Flexible communications 未知

    公开(公告)号：GB201118412D0

    公开(公告)日：2011-12-07

    申请号：GB201118412

    申请日：2011-10-25

    Applicant: ST MICROELECTRONICS GRENOBLE 2 ,  ST MICROELECTRONICS PVT LTD

    Abstract: A method for transmitting data on a configurable bus of z physical links, including receiving input data on an input bus at at least one of a plurality of data rates, selecting a number of physical links n, amongst the z physical links, on which data is to be transmitted, selecting a clock frequency f at which the data is to be transmitted on the configurable bus, wherein the selections of n and f are based on information concerning the at least one of the plurality of data rates, the number of links used on the input bus.

    39.
    发明专利
    未知

    公开(公告)号：DE60330834D1

    公开(公告)日：2010-02-25

    申请号：DE60330834

    申请日：2003-11-10

    Applicant: ST MICROELECTRONICS PVT LTD

    Inventor： SAHA KAUSHIK ,  MAITI SRIJIB NARAYAN

    IPC: H03H17/06 ,  G06F7/38 ,  H03H17/02

    Abstract: The present invention provides an improved Finite Impulse Response (FIR) filter providing linear scalability and implementation without the need for delay lines, comprising a multiprocessor architecture including a plurality of ALUs (Arithmetic and Logic Units), multipliers units, data cache, and load/store units sharing a common instruction cache, and multi-port memory, and an assigning means for assigning to each available processing unit the computation of specified unique partial product terms and the accumulation of each computed partial product on specified output sample values. A method is also provided for implementing an improved Finite Impulse Response (FIR) filter providing linear scalability using a multiprocessing architecture platform without the need for delay lines.

    40.
    发明专利
    未知

    公开(公告)号：DE602005016519D1

    公开(公告)日：2009-10-22

    申请号：DE602005016519

    申请日：2005-12-30

    Applicant: ST MICROELECTRONICS PVT LTD

    Inventor： GUPTA RANJEET ,  GARG PARAS

    IPC: H03K19/003 ,  H03K17/16

    Abstract: The invention relates to a low noise output buffer capable of operating at high speeds which allows a control of the slew rate at the raising and falling edges of an input signal (A) of the buffer. The proposed low noise output buffer (5) is inserted between first and second voltage references (VDD, GND) and comprises a main circuit (50) for which the slew rate of an input signal (A) is to be controlled, the main circuit (50) being connected to a slew rate control circuit (52), in turn inserted between the first and second voltage references (VDD, GND). Advantageously according to the invention, the slew rate control circuit (52) comprises an additional circuit (51) connected to the main circuit (50) and operating a slew rate limiting at the raising and falling edges of the input signal (A) of the low noise output buffer (5).

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