4.
    发明专利
    未知

    公开(公告)号:DE60134870D1

    公开(公告)日:2008-08-28

    申请号:DE60134870

    申请日:2001-12-28

    Abstract: The invention relates to a programming method of a multilevel memory cell able to store a plurality of bits in a plurality of levels (N), the method comprising at least a step of writing a logic value in the multilevel memory cell by setting one of the programming levels (LA) thereof, these levels being included in the plurality of levels (N), with respect to a reference level (LR) according to the symbol to be written and to a previous programming level. The writing step is repeated until a highest possible value (Lmax) for the levels (LS, LR) is reached. The invention relates also to a multilevel memory device comprising a plurality of multilevel memory cells organised into sectors, split into a plurality of data units (UD) whereon a programming operation is performed in parallel according to the method of the invention.

    7.
    发明专利
    未知

    公开(公告)号:DE69828966D1

    公开(公告)日:2005-03-17

    申请号:DE69828966

    申请日:1998-09-15

    Abstract: The method includes restoring the charge lost from memory cells, such as to restore the original voltage levels, within a time equivalent to the retention time. The decision concerning when the memory is to be restored is taken for example when the memory is switched on, based on the time elapsed since the previous programming/restoration, or based on the difference between the present threshold voltage of the reference cells and the original threshold voltage of the (suitably stored) reference cells, or when predetermined operating conditions occur. This makes it possible to prolong the life of nonvolatile memories, in particular of multilevel type, wherein the retention time decreases as the number of levels (bits/cell) is increased.

    10.
    发明专利
    未知

    公开(公告)号:DE60102203D1

    公开(公告)日:2004-04-08

    申请号:DE60102203

    申请日:2001-12-13

    Abstract: It is described a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels. The method comprises the phases of: initially programming a cell threshold value to a first set of levels [0;(m-1)] being m a submultiple of the plurality of levels of the multilevel cell; reprogramming without erasing another set of levels [m;(2m-1)] containing the same number m of levels as the first set; reiterating the reprogramming without erasing phase until the levels of the multilevel cell are exhausted. It is also described a multilevel memory device of the type comprising a plurality of multilevel memory cells organized into sectors, the sectors being themselves split into a plurality of data units wherein a data updating operation is performed in parallel, the data units being programmed by means of the programming method.

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