公开(公告)号：KR1020070109694A

公开(公告)日：2007-11-15

申请号：KR1020060043035

申请日：2006-05-12

Applicant: 삼성전자주식회사

Inventor： 오정민 ,  한정남 ,  홍창기 ,  이근택 ,  강대혁 ,  심우관 ,  이종원

IPC: H01L27/115

CPC classification number: H01L27/115 ,  H01L21/76229 ,  H01L27/11568 ,  H01L21/28282

Abstract: A method for manufacturing a SONOS(Silicon Oxide Nitride Oxide Semiconductor) type non-volatile memory device is provided to prevent plasma-etching damage and to improve charge trap characteristics by using a silicon nitride layer having a charge trap layer pattern. A trench is formed on a substrate(100). The trench is buried sufficiently and an isolation layer(108) is formed on the substrate. A first thin film including an insulating material is formed on the substrate which is exposed by the isolation layer. A second thin film pattern including silicon nitride is formed on the first thin film. A third thin film as a dielectric layer is formed on the resultant structure including the second thin film pattern and the isolation layer. A fourth thin film including a conductive material is formed on the third thin film. A gate structure(150) including a tunnel insulating layer pattern of the first thin film, a charge trap layer pattern of the second thin film pattern, a blocking insulating layer pattern of the third thin film, and a gate electrode of the fourth thin film is formed by patterning the four thin film, the third thin film, the second thin film pattern, and the first thin film. A source/drain(130) is formed under the surface of the substrate adjacent to the gate structure.

Abstract translation: 提供一种用于制造SONOS（氧化硅氮化物半导体）型非易失性存储器件的方法，以通过使用具有电荷陷阱层图案的氮化硅层来防止等离子体蚀刻损伤并改善电荷陷阱特性。 在衬底（100）上形成沟槽。 沟槽被充分地埋入，并且在衬底上形成隔离层（108）。 在由隔离层露出的基板上形成包括绝缘材料的第一薄膜。 在第一薄膜上形成包括氮化硅的第二薄膜图案。 在包括第二薄膜图案和隔离层的所得结构上形成作为电介质层的第三薄膜。 在第三薄膜上形成包括导电材料的第四薄膜。 包括第一薄膜的隧道绝缘层图案，第二薄膜图案的电荷陷阱层图案，第三薄膜的阻挡绝缘层图案和第四薄膜的栅电极的栅极结构（150） 通过对四个薄膜，第三薄膜，第二薄膜图案和第一薄膜进行图案化而形成。 源极/漏极（130）形成在与栅极结构相邻的衬底的表面下方。

公开(公告)号：KR100660880B1

公开(公告)日：2006-12-26

申请号：KR1020050096165

申请日：2005-10-12

Applicant: 삼성전자주식회사

Inventor： 강대혁 ,  오정민 ,  홍창기 ,  최상준 ,  심우관

IPC: H01L27/108

Abstract: A method for manufacturing a semiconductor memory device is provided to restrain the bridge between adjacent storage node electrodes and to prevent the generation of voids in a lower material of the storage node electrode. A mold insulating layer with a plurality of holes is formed on a semiconductor substrate(105). A plurality of storage node electrodes(140) are formed in the plurality of holes, respectively. A capping layer(145) for exposing partially the mold insulating layer to the outside is formed on the resultant structure. The storage node electrodes are exposed to the outside through sidewalls by removing selectively the mold insulating layer from the resultant structure using a wet etching process. Then, the storage node electrodes are exposed to the outside through upper surfaces by removing the capping layer from the resultant structure using a dry etching process.

Abstract translation: 提供一种用于制造半导体存储器件的方法，以限制相邻存储节点电极之间的桥并防止在存储节点电极的下层材料中产生空隙。 在半导体衬底（105）上形成具有多个孔的模具绝缘层。 多个存储节点电极（140）分别形成在多个孔中。 在所得结构上形成用于部分地将模具绝缘层暴露于外部的覆盖层（145）。 通过使用湿法蚀刻工艺从所得结构中选择性地去除模具绝缘层，存储节点电极通过侧壁暴露于外部。 然后，通过使用干法蚀刻工艺从所得结构去除覆盖层，存储节点电极通过上表面暴露于外部。