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公开(公告)号：KR1020120081654A
公开(公告)日：2012-07-20
申请号：KR1020100126890
申请日：2010-12-13
Applicant: 삼성전자주식회사
IPC: G03F1/76 , H01L21/027
CPC classification number: B82Y10/00 , G03F1/46 , G03F1/48 , G03F1/50 , G03F1/54 , G03F1/68 , G03F1/80 , G03F1/76 , H01L21/0274 , H01L21/0337
Abstract: PURPOSE: A photo-mask and a method for manufacturing the same are provided to improve the reliability of a semiconductor device manufacturing process by being repeatedly used without the line width change of patterns. CONSTITUTION: A method for manufacturing a photo-mask includes the following: a light shielding pattern(115) and a reflection preventive film pattern(125) are successively stacked on a transparent substrate(100). The light shielding pattern is based on at least one of chrome(Cr), aluminum(Al), rubidium(Ru), tantalum(Ta), tantalum boron oxide(TaBO), and tantalum boron nitride(TaBN). The sidewall of the light shielding pattern is oxidized and nitrided to form a protective film pattern(135) based on plasma treatment. The plasma treatment uses oxygen gas and nitrogen gas as reactive gas. The mixed ratio of the oxygen gas and the nitrogen gas is in a range between 5 and 8. The temperature of a chamber for the plasma treatment is kept in a range between 200 and 400 degrees Celsius.
Abstract translation: 目的：提供一种光掩模及其制造方法，以通过在没有图案的线宽变化的情况下重复使用来提高半导体器件制造工艺的可靠性。 构成：用于制造光掩模的方法包括以下：在透明基板（100）上依次层叠遮光图案（115）和防反射膜图案（125）。 遮光图案基于铬（Cr），铝（Al），铷（Ru），钽（Ta），钽氧化硼（TaBO）和钽氮化硼（TaBN）中的至少一种。 基于等离子体处理，遮光图案的侧壁被氧化并氮化以形成保护膜图案（135）。 等离子体处理使用氧气和氮气作为反应气体。 氧气和氮气的混合比在5和8之间。用于等离子体处理的室的温度保持在200和400摄氏度之间的范围内。
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公开(公告)号：KR1020100083629A
公开(公告)日：2010-07-22
申请号：KR1020090003104
申请日：2009-01-14
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7881 , H01L21/76224
Abstract: PURPOSE: A method for manufacturing a nonvolatile memory device is provided to uniformly form a sidewall profile of a stack structure by using materials with impurity content difference as first and second material films. CONSTITUTION: A first material film(110) and a second material film(120) are alternately laminated on a semiconductor substrate(100). Trenches passing through the first and second material films are formed by performing a first etching process. The second material films exposed to the trench are removed by performing a second etching process. The first and second material layers are made of the material with impurity content difference.
Abstract translation: 目的：提供一种用于制造非易失性存储器件的方法，通过使用具有杂质含量差的材料作为第一和第二材料膜来均匀地形成堆叠结构的侧壁轮廓。 构成：在半导体衬底（100）上交替层叠第一材料膜（110）和第二材料膜（120）。 通过第一和第二材料膜的沟槽通过执行第一蚀刻工艺而形成。 通过进行第二蚀刻工艺去除暴露于沟槽的第二材料膜。 第一和第二材料层由具有杂质含量差异的材料制成。
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公开(公告)号：KR100807226B1
公开(公告)日：2008-02-28
申请号：KR1020060078837
申请日：2006-08-21
Applicant: 삼성전자주식회사
IPC: H01L21/8242 , H01L27/108
CPC classification number: H01L28/91 , H01L27/10814 , H01L27/10817 , H01L27/10852
Abstract: 반도체 장치의 제조 방법에서, 패드 영역을 갖는 기판 상에 질화물을 포함하는 식각 저지막 및 산화물을 포함하는 몰드막이 형성된다. 상기 몰드막 및 식각 저지막을 패터닝하여 상기 기판의 패드 영역을 노출시키는 개구를 형성한다. 황산(H
2 SO
4 ) 및 물(H
2 O)을 포함하는 식각액을 이용하여 상기 개구에 의해 노출된 상기 식각 저지막의 측면 부위를 식각함으로써 상기 식각 저지막에 의해 한정된 개구의 하부를 상기 몰드막에 의해 한정된 개구의 중앙 부위보다 넓게 확장시킨다. 이어서, 상기 확장된 개구의 표면들 상에 하부 전극을 형성하고, 상기 하부 전극 상에 유전막 및 상부 전극을 형성하여 커패시터를 완성한다. 상기와 같이 하부가 확장된 개구 내에 하부 전극을 형성하므로 상기 커패시터의 구조적 안정성이 향상될 수 있다.Abstract translation: 在制造半导体器件的方法中，在具有焊盘区域的衬底上形成包括氧化物的模制膜和包含氮化物的蚀刻停止膜。 模制膜和蚀刻停止膜被图案化以形成暴露衬底的焊盘区域的开口。 硫酸（H
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公开(公告)号：KR101650025B1
公开(公告)日：2016-08-23
申请号：KR1020100002838
申请日：2010-01-12
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L49/02
Abstract: 커패시터형성방법및 이를이용한디램소자제조방법에서, 상기커패시터를형성하기위하여기판상에제1 절연물질을사용하여상부면에트렌치가생성된제1 몰드막패턴을형성한다. 상기트렌치내부에상기제1 절연물질과식각선택성을갖는제2 절연물질을사용하여지지막패턴을형성한다. 상기제1 몰드막패턴및 지지막패턴상에제2 몰드막을형성한다. 상기제2 몰드막및 제1 몰드막패턴을관통하고, 상기지지막패턴에의해지지되는하부전극을형성한다. 상기제1 몰드막패턴및 제2 몰드막을선택적으로제거한다. 상기하부전극및 지지막패턴상에유전막및 상부전극을형성한다. 상기방법에의하면, 안정적인구조의커패시터를형성할수 있다.
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公开(公告)号：KR1020120003677A
公开(公告)日：2012-01-11
申请号：KR1020100064410
申请日：2010-07-05
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/11578 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11575 , H01L27/11582 , H01L21/28273 , H01L21/67075 , H01L27/0207 , H01L27/0688
Abstract: PURPOSE: A semiconductor device and a formation method thereof are provided to apply one or more wet etching processes and a single photo process exposing a second region, thereby arranging conductive patterns in a step structure with a low price. CONSTITUTION: A substrate(110) comprises a first region(R1) and a second region(R2) which is located adjacent to the first region. A well region(112) is arranged by supplying impurity ions of a first conductive type within the substrate of the first region. A first material film(123) and a second material film(125) which are different from each other are arranged in order to be alternatively laminated on the substrate. A mask pattern exposing a partial area of the second region is arranged on a material film of the uppermost layer. The first material films and second material films in the partial area exposed by the mask pattern are wet etched in order to arrange a step type laminated pattern in which lateral and upper surfaces of the second material films are exposed.
Abstract translation: 目的：提供一种半导体器件及其形成方法，以应用一个或多个湿蚀刻工艺和暴露第二区域的单一照相工艺，从而以低价格布置阶梯结构中的导电图案。 构成：衬底（110）包括位于第一区域附近的第一区域（R1）和第二区域（R2）。 通过在第一区域的衬底内提供第一导电类型的杂质离子来布置阱区域（112）。 布置彼此不同的第一材料膜（123）和第二材料膜（125），以交替层压在基板上。 暴露第二区域的局部区域的掩模图案布置在最上层的材料膜上。 对通过掩模图案曝光的部分区域中的第一材料膜和第二材料膜进行湿式蚀刻，以便布置其中暴露第二材料膜的侧表面和上表面的阶梯型叠层图案。
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Patent Agency Ranking
公开(公告)号：KR1020110082901A
公开(公告)日：2011-07-20
申请号：KR1020100002838
申请日：2010-01-12
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L49/02
CPC classification number: H01L27/10847 , H01L27/10805 , H01L28/40
Abstract: PURPOSE: A method for forming a capacitor and a method for manufacturing a dram device using the same are provided to adjust the thicknesses of mold films, thereby easily changing the location of a support film pattern. CONSTITUTION: A first mold film pattern includes a trench on a substrate(100). A supporting film pattern(116) is formed in the trench using a second insulating material. A second mold film is formed on the first mold film pattern and the supporting film pattern. A lower electrode(112) contacts a sidewall of the supporting film pattern. A dielectric film(118) and an upper electrode(120) are formed on the lower electrode and the supporting film pattern.
Abstract translation: 目的：提供一种形成电容器的方法和使用该电容器的电容器的制造方法，以调节模具膜的厚度，从而容易地改变支撑膜图案的位置。 构成：第一模具薄膜图案包括在基底（100）上的沟槽。 使用第二绝缘材料在沟槽中形成支撑膜图案（116）。 在第一模具薄膜图案和支撑薄膜图案上形成第二模具薄膜。 下电极（112）接触支撑膜图案的侧壁。 在下电极和支撑膜图案上形成介电膜（118）和上电极（120）。
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公开(公告)号：KR1020090038590A
公开(公告)日：2009-04-21
申请号：KR1020070103959
申请日：2007-10-16
Applicant: 동우 화인켐 주식회사 , 삼성전자주식회사
CPC classification number: G03F7/425 , G03F1/103 , G03F7/063 , G03F7/30 , G03F7/32 , G03F7/34 , G03F7/422
Abstract: A photoresist stripper composition and a process of stripping photoresist by using the same are provided to cure or strip photoresist changed into a polymer after ion injection process and high temperature etching. A photoresist stripper composition comprises a mixture of sulfuric acid solution and hydrogen peroxide solution in which the weight ratio of pure sulfuric acid and pure hydrogen peroxide is 1~10,000:1; and an ammonium salt compound. The ammonium salt compound is a mixture of at least one or two selected from the group consisting of ammonium phosphate, ammonium sulfate, ammonium nitrate, ammonium borate, ammonium persulfate, ammonium citrate, ammonium oxalate, ammonium formate and ammonium carbonate.
Abstract translation: 提供光致抗蚀剂剥离剂组合物和通过使用其来剥离光致抗蚀剂的方法以在离子注入工艺和高温蚀刻之后固化或剥离变成聚合物的光致抗蚀剂。 光致抗蚀剂组合物包括硫酸溶液和过氧化氢溶液的混合物，其中纯硫酸和纯过氧化氢的重量比为1〜10,000:1; 和铵盐化合物。 铵盐化合物是选自磷酸铵，硫酸铵，硝酸铵，硼酸铵，过硫酸铵，柠檬酸铵，草酸铵，甲酸铵和碳酸铵中的至少一种或两种以上的混合物。
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公开(公告)号：KR1020080055118A
公开(公告)日：2008-06-19
申请号：KR1020060128048
申请日：2006-12-14
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/8242
CPC classification number: H01L28/91 , H01L27/10855
Abstract: A method for forming a semiconductor device is provided to prevent damage of a supporting structure in an oxide layer removal process. A second interlayer dielectric(115) is formed on a semiconductor substrate(100) including a first interlayer dielectric(105). A storage node insulating layer is formed on the second interlayer dielectric. An opening is formed by etching the storage node insulating layer and the second interlayer dielectric. A storage node(130) and a burial insulating layer(135) are formed within the opening. A supporting structure(120a) is formed by patterning the storage node insulating layer. A protective layer pattern is formed to cover the supporting structure. The insulating layer is removed. The protective pattern is removed.
Abstract translation: 提供一种用于形成半导体器件的方法，以防止在氧化物层去除过程中支撑结构的损坏。 在包括第一层间电介质（105）的半导体衬底（100）上形成第二层间电介质（115）。 存储节点绝缘层形成在第二层间电介质上。 通过蚀刻存储节点绝缘层和第二层间电介质形成开口。 存储节点（130）和埋藏绝缘层（135）形成在开口内。 通过图案化存储节点绝缘层来形成支撑结构（120a）。 形成保护层图案以覆盖支撑结构。 绝缘层被去除。 保护图案被去除。
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公开(公告)号：KR100794210B1
公开(公告)日：2008-01-11
申请号：KR1020060101159
申请日：2006-10-18
Applicant: 삼성전자주식회사
IPC: H01L21/304 , H01L21/306
CPC classification number: H01L21/31111 , H01L21/67086 , H01L21/76224
Abstract: A method and an apparatus for etching a semiconductor substrate are provided to prevent a teflon coating from being delaminated from a crystal bath by forming the teflon coating while burying a groove formed on an inner wall of the crystal bath. An apparatus for etching a semiconductor substrate includes a bath(110) and a coating layer(120). A chemical for etching the semiconductor substrate is contained in the bath, which includes plural grooves formed on an inner wall thereof. The coating layer is formed on the inner wall of the bath to fill in the grooves. The coating layer prevents a chemical reaction between the chemical and the bath. The bath is made of quartz. The coating layer is made of a teflon. A diameter of an inter hole of the groove is greater than that of a bottom thereof.
Abstract translation: 提供一种用于蚀刻半导体衬底的方法和装置，以防止聚四氟乙烯涂层通过在形成在晶体槽的内壁上的沟槽的同时形成聚四氟乙烯涂层而从晶体槽分层。 用于蚀刻半导体衬底的设备包括浴（110）和涂层（120）。 用于蚀刻半导体衬底的化学品包含在浴中，其包括形成在其内壁上的多个凹槽。 在镀液的内壁上形成涂层以填充凹槽。 涂层防止化学品和浴液之间发生化学反应。 浴缸是由石英制成。 涂层由聚四氟乙烯制成。 槽的孔的直径大于其底部的直径。
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公开(公告)号：KR101481104B1
公开(公告)日：2015-01-13
申请号：KR1020090004232
申请日：2009-01-19
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/792 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/7926
Abstract: 3차원 구조의 비휘발성 메모리 장치 및 그 제조 방법이 제공된다. 비휘발성 메모리 장치는 반도체 기판 상에 3차원적으로 배열된 도전 패턴들, 반도체 기판으로부터 연장되어 도전 패턴들의 일측벽들을 가로지르는 반도체 패턴들, 반도체 패턴과 도전 패턴의 일측벽 사이에 개재된 전하 저장막 및 전하 저장막과 도전 패턴의 일측벽 사이에 개재된 씨드막 패턴을 포함한다.
3차원, 씨드막 패턴, 전하 확산
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