公开(公告)号：KR1020100041139A

公开(公告)日：2010-04-22

申请号：KR1020080100174

申请日：2008-10-13

Applicant: 삼성전자주식회사

Inventor： 오규환 ,  안형근 ,  박순오 ,  안동호 ,  박영림

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/141 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1666 ,  H01L45/1683 ,  H01L21/31051 ,  H01L21/76229 ,  H01L45/143

Abstract: PURPOSE: A memory for manufacturing a multi-level cell for storing multiple bits data in one memory cell using a phase change material with three or more parallel structures is provided to identify resistance values by differentiating set resistance values based on the composition ratio and the kinds of the phase change material. CONSTITUTION: Three or more lower electrodes(220, 222, 224) are parallely formed on a contact plug(210). Three or more phase change materials(330, 332, 334) are parallely formed on the lower electrodes. The phase change materials correspond to the lower electrodes. An upper electrode is formed on the phase change materials. A part of the upper part of the lower electrodes is removed. The phase change materials are embedded in the removed space.

Abstract translation: 目的：提供一种用于使用具有三个或更多个并联结构的相变材料将多位数据存储在一个存储单元中的多级单元的存储器，以通过基于组成比和类型来区分设定电阻值来识别电阻值 的相变材料。 构成：三个或更多个下电极（220,222,224）平行地形成在接触插塞（210）上。 三个或更多个相变材料（330,332,334）平行地形成在下电极上。 相变材料对应于下部电极。 在相变材料上形成上电极。 去除下部电极的上部的一部分。 相变材料嵌入在移除的空间中。

公开(公告)号：KR1020080099459A

公开(公告)日：2008-11-13

申请号：KR1020070045014

申请日：2007-05-09

Applicant: 삼성전자주식회사

Inventor： 안형근 ,  안동호 ,  호리이히데키 ,  고한봉 ,  박영림

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/76877 ,  H01L21/28273 ,  H01L21/31144 ,  H01L21/67075

Abstract: A data store layer pattern having the small width than 100nm in the forming process can be not damaged, and the data store layer pattern can be steadily molded. Accordingly, the reliability and performance characteristic of the memory device including data store layer pattern can be improved. The first insulating layer(120) including the first conductive pattern(125) on the substrate(110) is formed. The laminated data store layer pattern(135), and the second conductive pattern(145) and sacrificial layer pattern are formed on the first conductive pattern. The second insulating layer(160) is formed on the sacrificial layer pattern. The second insulating layer is patterned and then the first hole to expose the sacrificial layer pattern is formed. The sacrificial layer pattern is removed, and then the second hole to expose the second conductive pattern is formed. The third conductive pattern(190) connected to the second conductive pattern within the first and second holes is formed.

Abstract translation: 在成形过程中，具有小于100nm的宽度的数据存储层图案可以不被损坏，并且可以稳定地模制数据存储层图案。 因此，可以提高包括数据存储层图案的存储装置的可靠性和性能特性。 形成包括在基板（110）上的第一导电图案（125）的第一绝缘层（120）。 层压数据存储层图案（135）和第二导电图案（145）以及牺牲层图案形成在第一导电图案上。 第二绝缘层（160）形成在牺牲层图案上。 图案化第二绝缘层，然后形成用于露出牺牲层图案的第一孔。 去除牺牲层图案，然后形成第二孔以露出第二导电图案。 形成连接到第一和第二孔内的第二导电图案的第三导电图案（190）。

公开(公告)号：KR1020080098237A

公开(公告)日：2008-11-07

申请号：KR1020070043664

申请日：2007-05-04

Applicant: 삼성전자주식회사

Inventor： 조성래 ,  배병재 ,  이진일 ,  박혜영 ,  박영림 ,  김락환

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1666

Abstract: A phase change material memory device and a method for forming the same are provided to reduce the contact area between the conductor and the phase change material layer. A phase change material memory device comprises the first insulating layer(60) which is provided to the top of the substrate and limits the opening(70); the first part provided to the bottom of the opening; the first conductor(95) including the second part which successively is provided from the first part along the side wall of opening; the variable resistance(113) which is connected to the second part of the first conductor and is provided along the side wall of opening; the second conductor provided on the variable resistance.

Abstract translation: 提供相变材料存储装置及其形成方法以减少导体与相变材料层之间的接触面积。 相变材料存储装置包括设置在基板的顶部并限制开口（70）的第一绝缘层（60）。 第一部分提供到开口的底部; 所述第一导体（95）包括沿着所述开口的侧壁从所述第一部分连续设置的所述第二部分; 所述可变电阻器（113）连接到所述第一导体的第二部分并沿着开口的侧壁设置; 第二导体提供在可变电阻上。

公开(公告)号：KR1020080026746A

公开(公告)日：2008-03-26

申请号：KR1020060091691

申请日：2006-09-21

Applicant: 삼성전자주식회사

Inventor： 배병재 ,  박영림 ,  안상엽 ,  조성래 ,  이진일 ,  박혜영 ,  임지은

IPC: H01L21/02

Abstract: A method for cleaning a deposition chamber is provided to improve operational efficiency of deposition equipment and to secure a stable process condition by reducing a cleaning process time. A wafer unloading process is performed to unload a wafer from a chamber for performing a deposition process under a predetermined deposition condition(10). A cleaning gas supply process is performed to supply a cleaning gas into the chamber without causing a change of deposition temperature and a change of process atmosphere(20). An excitation process is performed to excite the cleaning gas within the chamber(30). A reactant exhausting process is performed to exhaust a reactant by inducing a reaction between the excited cleaning gas and a deposit within the chamber(40).

Abstract translation: 提供了用于清洁沉积室的方法，以提高沉积设备的操作效率并通过减少清洗处理时间来确保稳定的工艺条件。 执行晶片卸载处理以在预定沉积条件（10）下从用于执行沉积工艺的室中卸载晶片。 执行清洁气体供应过程以将清洁气体供应到室中而不引起沉积温度的改变和处理气氛的变化（20）。 执行激发过程以激发腔室（30）内的清洁气体。 通过引发被激发的清洁气体与室（40）内的沉积物之间的反应来进行反应物排出过程以排出反应物。

公开(公告)号：KR100791077B1

公开(公告)日：2008-01-03

申请号：KR1020060126832

申请日：2006-12-13

Applicant: 삼성전자주식회사

Inventor： 박영림 ,  조성래 ,  배병재 ,  이진일 ,  박혜영 ,  임지은

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/148 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144 ,  H01L45/1691 ,  H01L21/76224

Abstract: A phase change memory device having a small transition volume and a method for forming the same are provided to reduce remarkably current necessary for converting the transition volume to a crystalline state or an amorphous state. A bottom electrode(75) is formed on a top surface of a substrate(51). An interlayer dielectric includes a contact hole for exposing the bottom electrode and is formed to cover the interlayer dielectric. A resistant material pattern(79) is formed to fill up the contact hole. A phase change pattern(77) is inserted between the resistant material pattern and the interlayer dielectric and is extended between the resistant material pattern and the bottom electrode. A top electrode(85) comes in contact with the phase change pattern. The resistant material pattern has a resistance higher than that of the phase change pattern. The top electrode is electrically connected through the phase change pattern to the bottom electrode.

Abstract translation: 提供具有小过渡体积的相变存储器件及其形成方法，以将过渡体积转换为结晶状态或非晶态所需的显着电流降低。 底部电极（75）形成在基板（51）的顶表面上。 层间电介质包括用于暴露底部电极的接触孔，并形成为覆盖层间电介质。 形成电阻材料图案（79）以填充接触孔。 相变图案（77）插入在电阻材料图案和层间电介质之间，并且在电阻材料图案和底部电极之间延伸。 顶部电极（85）与相变图案接触。 电阻材料图案具有比相变图案高的电阻。 顶部电极通过相变图案电连接到底部电极。

公开(公告)号：KR100717286B1

公开(公告)日：2007-05-15

申请号：KR1020060036209

申请日：2006-04-21

Applicant: 삼성전자주식회사

Inventor： 조성래 ,  이충만 ,  이진일 ,  임상욱 ,  박혜영 ,  박영림

IPC: H01L27/115

CPC classification number: H01L45/1233 ,  C23C16/305 ,  C23C16/45523 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1683

Abstract: 상변화 물질층의 형성 방법과, 그 방법을 이용한 상변화 기억 소자의 형성 방법 및 상변화 기억 소자를 제공한다. 본 발명에 따르면, 상변화 물질층을 선택적으로 형성함으로써, 보이드 및 심 없이 홀을 채우는 상변화 패턴을 구현할 수 있다. 이로써, 상변화 기억 소자의 특성 저하를 방지하고, 고집적화 및/또는 저소비전력화에 최적화된 상변화 기억 소자를 구현할 수 있다.