公开(公告)号：KR100599056B1

公开(公告)日：2006-07-12

申请号：KR1020050066374

申请日：2005-07-21

Applicant: 삼성전자주식회사

Inventor： 김인기 ,  황인석 ,  정대혁 ,  김경환

IPC: H01L21/027

公开(公告)号：KR1020040044091A

公开(公告)日：2004-05-27

申请号：KR1020030051206

申请日：2003-07-25

Applicant: 삼성전자주식회사

Inventor： 여인준 ,  고용선 ,  황인석 ,  윤병문 ,  정대혁 ,  김경현

IPC: H01L21/304

CPC classification number: C11D11/0047 ,  C11D7/06 ,  C11D7/265

Abstract: PURPOSE: A cleaning solution for a semiconductor device and a method for cleaning a semiconductor device are provided to clean a semiconductor substrate having an exposed aluminum pattern by using megasonic energy and the cleaning solution of ammonia water, acetic acid, and deionized water. CONSTITUTION: A cleaning solution for a semiconductor device is formed with ammonia water, acetic acid, and deionized water. The weight percent of the acetic acid is higher than the weight percent of the ammonia water. The weight percent of the deionized water is higher than the weight percent of the acetic acid. A ratio of the ammonia water, the acetic acid, and the deionized water is 1: 1 to 100: 1000 to 100000. The cleaning solution of the ammonia water, the acetic acid, and the deionized water has acidity below 6.5. A cleaning solution layer is formed by providing the cleaning solution on a semiconductor substrate having an exposed metal pattern(S100). The megasonic energy is provided to the cleaning solution layer(S120). The semiconductor substrate having the exposed metal pattern is cleaned(S140).

Abstract translation: 目的：提供一种用于半导体器件的清洁溶液和用于清洁半导体器件的方法，以通过使用兆声波能量和氨水，乙酸和去离子水的清洁溶液来清洁具有暴露的铝图案的半导体衬底。 构成：用氨水，乙酸和去离子水形成用于半导体器件的清洁溶液。 乙酸的重量百分比高于氨水的重量百分数。 去离子水的重量百分比高于乙酸的重量百分数。 氨水，乙酸和去离子水的比例为1:1至100:1000至100000.氨水，乙酸和去离子水的清洗溶液的酸度低于6.5。 通过在具有暴露的金属图案的半导体衬底上提供清洁溶液形成清洁溶液层（S100）。 将兆声波能量提供给清洁溶液层（S120）。 清洁具有暴露的金属图案的半导体衬底（S140）。

公开(公告)号：KR100338764B1

公开(公告)日：2002-05-30

申请号：KR1019990040379

申请日：1999-09-20

Applicant: 삼성전자주식회사

Inventor： 하헌재 ,  정대혁 ,  황인석 ,  고용선

IPC: H01L21/304

CPC classification number: C11D3/3947 ,  C11D7/08 ,  C11D7/10 ,  C11D11/0047 ,  H01L21/02063 ,  H01L21/76814 ,  H01L21/76897

Abstract: 불순물이도우프된절연막을손상시키지않고식각부산물또는식각에의해손상된실리콘막등을선택적으로제거할수 있는세정액및 이를이용한세정방법이제공된다. 본발명에따른세정액은불화수소 0.08 내지 0.1 중량%, 불화암모늄 0.5 내지 0.6 중량%, 과산화수소 24.9 내지 49.7 중량% 및물 49.6 내지 74.5 중량%를포함한다.

公开(公告)号：KR1020020032773A

公开(公告)日：2002-05-04

申请号：KR1020000063415

申请日：2000-10-27

Applicant: 삼성전자주식회사

Inventor： 최성길 ,  안태혁 ,  정상섭 ,  정대혁 ,  이원준

IPC: H01L27/108

CPC classification number: H01L28/91 ,  H01L21/3212 ,  Y10S438/949

Abstract: PURPOSE: A method for forming a cylinder type storage node of semiconductor equipment is provided to maintain uniformly capacitance of a capacitor by minimizing a difference of loss between conductive layers of a center portion and a peripheral portion of a cell region. CONSTITUTION: A poly plug(12) is formed on an interlayer dielectric(10). A nitride layer as an etching stopper is coated thereon. A molding oxide layer is formed on the nitride layer(14). A hole is formed on the molding oxide layer. A storage conductive layer is coated thereon. A charging material such as a photo-resist or a CVD oxide layer is deposited on the storage conductive layer. The photo-resist is removed by performing an etch back process. The storage conductive layer is separated by etching an exposed polysilicon. The remaining material and the molding oxide layer are removed from the hole by performing an ashing process or a wet etch process. A storage node(26) is formed by removing the remaining material and the molding oxide layer.

Abstract translation: 目的：提供一种用于形成半导体设备的圆筒型存储节点的方法，通过最小化中心部分的导电层与单元区域的周边部分之间的损耗差来维持电容器的均匀电容。 构成：多层塞子（12）形成在层间电介质（10）上。 在其上涂覆作为蚀刻停止层的氮化物层。 在氮化物层（14）上形成模制氧化物层。 在模制氧化物层上形成孔。 在其上涂覆存储导电层。 诸如光致抗蚀剂或CVD氧化物层的充电材料沉积在存储导电层上。 通过执行回蚀处理去除光致抗蚀剂。 通过蚀刻暴露的多晶硅来分离存储导电层。 通过灰化处理或湿蚀刻工艺从孔中去除剩余的材料和模制氧化物层。 通过去除剩余的材料和模制氧化物层来形成存储节点（26）。

公开(公告)号：KR1020000061508A

公开(公告)日：2000-10-25

申请号：KR1019990010577

申请日：1999-03-26

Applicant: 삼성전자주식회사

Inventor： 정대혁 ,  백인학

IPC: H01L21/76

Abstract: PURPOSE: A method for forming a trench isolation structure is to prevent a trench etching mask from remaining on an active area after the trench isolation is completed and to remove an anti-reflection film simultaneously with a trench cleaning process. CONSTITUTION: A method for forming a trench isolation structure comprises the steps of: a forming a trench(108) by using a trench etching mask including a silicon nitride film(104) and an anti-reflection film formed on a semiconductor substrate(100), and forming a pad oxide film(102) between the semiconductor substrate and the silicon nitride film; washing the trench and at the same time removing the anti-reflection film; forming a thermal oxide film in an inside wall of the trench; depositing a trench isolation film on the semiconductor substrate to completely fill up the trench; etching evenly the trench isolation film to expose the silicon nitride film; and sequentially removing the silicon nitride film and the pad oxide film to form a trench isolation structure.

Abstract translation: 目的：形成沟槽隔离结构的方法是在沟槽隔离完成之后防止沟槽蚀刻掩模残留在有源区上，并且与沟槽清洗工艺同时去除防反射膜。 构成：用于形成沟槽隔离结构的方法包括以下步骤：通过使用包括形成在半导体衬底（100）上的氮化硅膜（104）和抗反射膜的沟槽蚀刻掩模形成沟槽（108） 在半导体衬底和氮化硅膜之间形成衬垫氧化膜（102）; 洗涤沟槽并同时去除防反射膜; 在沟槽的内壁中形成热氧化膜; 在半导体衬底上沉积沟槽隔离膜以完全填满沟槽; 均匀地蚀刻沟槽隔离膜以暴露氮化硅膜; 并依次去除氮化硅膜和衬垫氧化物膜以形成沟槽隔离结构。

公开(公告)号：KR1019990015598A

公开(公告)日：1999-03-05

申请号：KR1019970037794

申请日：1997-08-07

Applicant: 삼성전자주식회사

Inventor： 정대혁

IPC: H01L21/304

Abstract: 불화 암모늄(NH
4 F)과 IPA(isopropyl alcohol: (CH
3 )
2 CH
2 OH)가 1:1 ∼ 1:50의 부피비로 혼합된 혼합액으로 이루어지는 세정액 및 이를 이용한 콘택홀 세정 방법에 관하여 개시한다. 본 발명에서는 반도체 기판상에 서로 다른 종류의 복수의 산화막을 차례로 적층한다. 상기 복수의 산화막을 동시에 패터닝하여 상기 반도체 기판의 소정 영역을 노출시키는 콘택홀을 형성한다. 상기 콘택홀이 형성된 결과물을 불화 암모늄과 IPA가 1:1 ∼ 1:50의 부피비로 혼합된 혼합액으로 소정 시간 동안 세정한다.

公开(公告)号：KR1019980084291A

公开(公告)日：1998-12-05

申请号：KR1019970020044

申请日：1997-05-22

Applicant: 삼성전자주식회사

Inventor： 정대혁

IPC: H01L21/306

Abstract: 금속층 패턴 형성 후의 세정방법에 대해 개시된다. 이 방법은, 금속층 패턴 형성 후의 세정방법에 있어서 NH
4 OH, TMAH, 및 EG의 용액을 적정량 혼합한 혼합 세정액을 사용하는 것을 특징으로 한다. 이에 따라, 종래의 세정액 NH
4 OH에 TMAH 및 EG를 혼합하여 사용함으로써 금속층 패턴 형성시 발생되는 폴리머를 효과적으로 제거할 수 있고, 금속과 세정액간의 작용을 최소화 할 수 있다.

公开(公告)号：KR1019980005740A

公开(公告)日：1998-03-30

申请号：KR1019960023951

申请日：1996-06-26

Applicant: 삼성전자주식회사

Inventor： 권영민 ,  윤병문 ,  정대혁

IPC: H01L21/304

公开(公告)号：KR1020130142738A

公开(公告)日：2013-12-30

申请号：KR1020120066231

申请日：2012-06-20

Applicant: 삼성전자주식회사

Inventor： 최상현 ,  노진호 ,  손윤호 ,  정대혁 ,  황인석 ,  박태준 ,  황태호

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/76841 ,  H01L21/28158 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/66621

Abstract: The present invention relates to a methods of fabricating semiconductor devices forming a first preliminary gate barrier film and a first preliminary gate electrode recessed from the surface of a substrate in a gate trench in a first depth; forming a second preliminary gate electrode recessed in a second depth, which is deeper than the first depth, by eliminating the upper part of the first preliminary gate electrode through performing a first wet etching process using a first etching liquid; and forming a gate electrode and gate barrier film recessed in a third depth, which is deeper than the second depth, by eliminating the upper part of the second preliminary gate electrode and the upper part of the first preliminary gate barrier film through performing a second wet etching process using a second etching liquid.

Abstract translation: 本发明涉及制造半导体器件的方法，所述半导体器件形成第一初步栅极阻挡膜和在第一深度的栅极沟槽中从衬底表面凹陷的第一初级栅电极; 通过使用第一蚀刻液进行第一湿法蚀刻处理，形成第二预备栅电极，该第二预选栅电极比第一深度深，通过消除第一预选栅电极的上部， 以及通过以下步骤形成栅极电极和栅极阻挡膜，所述栅电极和栅极阻挡膜比第二深度更深地凹陷，所述第三深度比第二深度更深，通过进行第二湿度除去第二预选栅电极的上部和第一预栅极阻挡膜的上部 使用第二蚀刻液的蚀刻工艺。

公开(公告)号：KR1020120011431A

公开(公告)日：2012-02-08

申请号：KR1020100073212

申请日：2010-07-29

Applicant: 삼성전자주식회사

Inventor： 손윤호 ,  이몽섭 ,  황인석 ,  정대혁 ,  최석헌 ,  이상준

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L27/108 ,  H01L29/10 ,  H01L23/485

CPC classification number: H01L27/10888 ,  H01L21/02057 ,  H01L21/02063 ,  H01L21/30608 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10814 ,  H01L27/10855 ,  H01L29/1037 ,  H01L29/41766 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A memory device and a manufacturing method thereof are provided to arrange a silicon recess which has a multi-facet type three-dimensional shape on the surface of an active region, thereby improving a contact area of a contact structure. CONSTITUTION: A substrate(10) comprises a field region and an active region. The substrate comprises a silicon recess(12) which is connected to a contact hole in a part of the active region. An insulating film(20) is arranged on the substrate in order to cover conductive structures. The insulating film comprises the contact hole(22) which partially exposes the substrate. A conductive pattern(30) buries the contact hole.

Abstract translation: 目的：提供一种存储器件及其制造方法，用于在有源区域的表面上布置具有多面型三维形状的硅凹槽，从而改善接触结构的接触面积。 构成：衬底（10）包括场区域和有源区域。 该衬底包括与有源区的一部分中的接触孔连接的硅凹部（12）。 绝缘膜（20）布置在基板上以覆盖导电结构。 绝缘膜包括部分地暴露衬底的接触孔（22）。 导电图案（30）埋入接触孔。