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公开(公告)号：KR1020040038379A
公开(公告)日：2004-05-08
申请号：KR1020020067280
申请日：2002-10-31
Applicant: 한국전자통신연구원
IPC: H01L29/737
Abstract: PURPOSE: A smart power device with a built-in silicon germanium HBT(hetero-junction bipolar transistor) is provided to embody a high voltage tolerance greater than 100 voltage by effectively distributing a drain electric filed, to satisfy an ultra high speed and a high voltage tolerance by using an epi layer of 1.5 micro meter class, and to improve integration by using a trench isolation technology. CONSTITUTION: A substrate(31) is prepared in which an oxygen ion implantation layer with an open space is formed between two semiconductor layers. A silicon germanium HBT is formed on the substrate. A CMOS(complementary metal oxide semiconductor) device is formed on the substrate. A bipolar device is formed on the substrate. An LDMOS(lateral double diffused metal oxide semiconductor) device is formed on the substrate.
Abstract translation: 目的：通过有效分配漏极电场，提供内置硅锗HBT（异质结双极晶体管）的智能功率器件，以实现大于100的高电压容限，以满足超高速和高速 通过使用1.5微米级的外延层进行电压容限，并通过使用沟槽隔离技术改善集成度。 构成：制备其中在两个半导体层之间形成具有开放空间的氧离子注入层的衬底（31）。 在基板上形成硅锗HBT。 在基板上形成CMOS（互补金属氧化物半导体）器件。 在基板上形成双极器件。 在基板上形成LDMOS（横向双扩散金属氧化物半导体）器件。
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公开(公告)号：KR1020030023286A
公开(公告)日：2003-03-19
申请号：KR1020010056434
申请日：2001-09-13
Applicant: 한국전자통신연구원
IPC: H01L21/28
Abstract: PURPOSE: A semiconductor device having a metal wiring layer completely buried in a hole and fabrication method by using a selective nitridation process are provided to prevent generation of a void and a short circuit when the metal line layer is buried into a contact hole or a via hole. CONSTITUTION: A hole(104) and an interlayer dielectric(103) are formed on a semiconductor substrate(101). The first material layer pattern(105a) is formed on an inner wall and a bottom of the hole(104) and the interlayer dielectric(103). The second material layer pattern(109a) is formed on the first material layer pattern(105a). A metal line layer is formed by burying sequentially the first metal layer pattern(111a), the second metal layer pattern(113a), the third metal layer pattern(115a), and the fourth metal layer pattern(117a) into the hole(104).
Abstract translation: 目的：提供一种将金属布线层完全埋入孔中的半导体器件，并且通过使用选择性氮化处理的制造方法来防止当金属线层埋入接触孔或通孔中时产生空隙和短路 孔。 构成：在半导体基板（101）上形成有孔（104）和层间电介质（103）。 第一材料层图案（105a）形成在孔（104）和层间电介质（103）的内壁和底部上。 第二材料层图案（109a）形成在第一材料层图案（105a）上。 通过将第一金属层图案（111a），第二金属层图案（113a），第三金属层图案（115a）和第四金属层图案（117a）依次埋入孔（104）中而形成金属线层 ）。
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公开(公告)号：KR101700992B1
公开(公告)日：2017-01-31
申请号：KR1020130045492
申请日：2013-04-24
Applicant: 한국전자통신연구원
IPC: H01L27/115 , H01L21/8247
Abstract: 비휘발성메모리및 비휘발성메모리의제조방법이개시된다. 일실시예에따른비휘발성메모리는, 기판에형성된딥 웰(Deep Well); 상기딥 웰영역내에형성된제1 웰; 상기딥 웰영역내에상기제1 웰과이격되어형성된제2 웰; 상기제1 웰상에형성된제1 MOSFET; 및상기제2 웰상에형성된제2 MOSFET을포함할수 있다. 일실시예에따른비휘발성메모리의제조방법은, 컨트롤 MOSFET의웰 영역을인접한메모리셀의컨트롤 MOSFET의웰 영역과공유시키거나, 터널링 MOSFET의웰 영역을인접한메모리셀의터널링 MOSFET의웰 영역과공유시킴으로써, 메모리셀의면적을줄일수 있다. 또한, 일실시예에따른비휘발성메모리는, 터널링 MOSFET에있어서공유된웰 영역의전압을일정하게유지하고, 소스/드레인의전압을인접한셀과다르게함으로써웰 영역을공유하면서도선택한메모리셀에만데이터를기록하거나또는, 기록된데이터를지울수 있다.
Abstract translation: 公开了非易失性存储器和非易失性存储器制造方法。 在本发明的一个实施例中，非易失性存储器包括：在衬底上形成的深阱; 在深井区形成的第一口井; 第二井，其形成在深井区域并与第一井分离; 形成在第一阱上的第一MOSFET; 以及形成在第二阱上的第二MOSFET。 在该实施例中，非易失性存储器制造方法能够通过与相邻存储器单元的控制MOSFET共享控制MOSFET的阱区域或者使用隧道MOSFET的隧道MOSFET的阱区域来减小存储单元面积 的相邻存储单元。 此外，在本实施例中，通过保持共享阱区域的电压并且不同地施加源极和漏极电压，尽管通过共享井区域，但是仅在非易失性存储器的所选择的存储单元中记录数据或记录数据被删除 来自相邻单元的源极和漏极电压。
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公开(公告)号：KR1020160116294A
公开(公告)日：2016-10-07
申请号：KR1020160018592
申请日：2016-02-17
Applicant: 한국전자통신연구원
IPC: H01L29/872 , H01L29/47 , H01L29/66 , H01L21/285
Abstract: 기판, 상기기판상에배치되는드리프트층, 상기활성영역및 상기주변영역의경계상에배치되는접합마감층(junction termination layer), 상기활성영역의일부및 상기접합마감층의일부를덮는제 1 금속층, 및상기제 1 금속층및 상기활성영역을덮는제 2 금속층을포함하는쇼트키다이오드를제공하되, 상기드리프트층은활성영역(active region) 및상기활성영역외각에위치하는주변영역(periphery)을포함하고, 상기제 1 금속층및 상기제 2 금속층은상기드리프트층과접촉하여쇼트키(schottky) 접합을형성하고, 상기제 1 금속층은상기제 2 금속층보다더 높은쇼트키전위장벽(schottky barrier height)을가질수 있다.
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公开(公告)号：KR1020140092209A
公开(公告)日：2014-07-23
申请号：KR1020130129431
申请日：2013-10-29
Applicant: 한국전자통신연구원
IPC: H01L29/08
Abstract: The present invention provides a structure of a semiconductor power rectifying device. The structure of the semiconductor power rectifying device includes a first conductivity type doped substrate; a second electrode which is provided on the lower surface of the substrate; an active region and a field region which are defined on the substrate; a gate which is provided on the active region; a gate insulating layer which is provided between the gate and the substrate; body regions which are provided in the substrate adjacent to the first and second sides of the gate which face each other and are doped with the dopant of a second conductivity type which is different from the first conductivity type; and a plug region of a second conductivity type which is formed in the substrate adjacent to the third and the forth sides of the gate which connect the first and the second sides.
Abstract translation: 本发明提供一种半导体功率整流装置的结构。 半导体功率整流装置的结构包括第一导电型掺杂衬底; 设置在基板的下表面上的第二电极; 限定在所述基板上的有源区域和场区域; 设置在有源区上的栅极; 栅极绝缘层，其设置在所述栅极和所述基板之间; 本体区域设置在与栅极的第一和第二侧相邻的衬底中，所述第一和第二侧彼此面对并且掺杂有与第一导电类型不同的第二导电类型的掺杂物; 以及第二导电类型的插塞区域，其形成在与栅极的连接第一和第二侧面的第三和第四侧相邻的基板中。
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Patent Agency Ranking36.发明授权
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公开(公告)号：KR101386241B1
公开(公告)日：2014-04-17
申请号：KR1020100096841
申请日：2010-10-05
Applicant: 한국전자통신연구원
Abstract: 본 발명은 무기발광소자 및 그 제조방법에 관한 것으로, 무기발광소자에 있어서, 기 설정된 간격을 갖도록 주기적으로 배치된 구조를 갖는 패턴된 금속전극; 및 상기 패턴된 금속전극의 상부에 위치하는 형광층을 포함하며, 상기 패턴된 금속전극이 배치된 순서에 따라 양극과 음극이 교대로 인가됨에 따라 상기 형광층에서 발광한 빛이 상기 패턴된 금속전극의 사이로 방출되는 것을 특징으로 한다.
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公开(公告)号：KR1020130121737A
公开(公告)日：2013-11-06
申请号：KR1020130045492
申请日：2013-04-24
Applicant: 한국전자통신연구원
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L21/823892 , G11C16/30 , H01L21/823871 , H01L27/11521
Abstract: Non-volatile memory and a non-volatile memory manufacturing method are disclosed. In one embodiment of the present invention, the non-volatile memory comprises: a deep well formed on a substrate; a first well formed in the deep well region; a second well which is formed in the deep well region and separated from the first well; a first MOSFET formed on the first well; and a second MOSFET formed on the second well. In the embodiment, the non-volatile memory manufacturing method is able to reduce a memory cell area by sharing a well area of a control MOSFET with a control MOSFET of an adjacent memory cell, or a well area of a tunneling MOSFET with a tunneling MOSFET of an adjacent memory cell. Also, in the embodiment, data is recorded or recorded data is deleted only in a selected memory cell of the non-volatile memory, although a well area is shared, by maintaining the voltage of the shared well area and applying source and drain voltages differently from source and drain voltages of an adjacent cell.
Abstract translation: 公开了非易失性存储器和非易失性存储器制造方法。 在本发明的一个实施例中，非易失性存储器包括：在衬底上形成的深阱; 在深井区形成的第一口井; 第二井，其形成在深井区域并与第一井分离; 形成在第一阱上的第一MOSFET; 以及形成在第二阱上的第二MOSFET。 在该实施例中，非易失性存储器制造方法能够通过与相邻存储器单元的控制MOSFET共享控制MOSFET的阱区域或者使用隧道MOSFET的隧道MOSFET的阱区域来减小存储单元面积 的相邻存储单元。 此外，在本实施例中，通过保持共享阱区域的电压并且不同地施加源极和漏极电压，尽管通过共享井区域，但是仅在非易失性存储器的所选择的存储单元中记录数据或记录数据被删除 来自相邻单元的源极和漏极电压。
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公开(公告)号：KR1020130067907A
公开(公告)日：2013-06-25
申请号：KR1020110134949
申请日：2011-12-14
Applicant: 한국전자통신연구원
CPC classification number: H02J50/00 , H04B5/0037 , Y02D70/00
Abstract: PURPOSE: An active wireless power apparatus which has an energy harvest function and a method thereof are provided to supply power to reduce power consumption of a wireless communication device, to enable the wireless communication device to be operated mainly in a power down mode state, and to supply power to the wireless communication device when communications are required. CONSTITUTION: An active wireless power apparatus includes a gathering unit(21) which receives a radio signal of light or frequency which is transmitted from the outside, and a power generation unit(22) which processes a signal which is outputted through the gathering unit, and outputs a fixed level of a voltage signal. A wireless communication device, which is in a power down mode, is woken up and operated in an operation mode according to the voltage signal. [Reference numerals] (12) Matching unit; (13) RF signal processing unit; (14) Battery; (21) Gathering unit; (22) Power generation unit; (23) Switch unit; (3) Reader; (AA) Frequency & Light
Abstract translation: 目的：提供具有能量收集功能的有源无线电力装置及其方法，以提供功率以减少无线通信装置的功耗，使得无线通信装置主要以断电模式状态运行，以及 当需要通信时向无线通信设备供电。 构成：有源无线电力装置包括：接收从外部发送的光或频率的无线电信号的收集单元（21），以及处理通过收集单元输出的信号的发电单元（22） 并输出电压信号的固定电平。 处于断电模式的无线通信装置根据电压信号被唤醒并在操作模式下操作。 （附图标记）（12）匹配单元; （13）射频信号处理单元; （14）电池; （21）收集单位; （22）发电机组; （23）开关单元; （3）读者; （AA）频率与光
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公开(公告)号：KR101215304B1
公开(公告)日：2012-12-26
申请号：KR1020090105358
申请日：2009-11-03
Applicant: 한국전자통신연구원
IPC: H01L21/027
CPC classification number: G03F7/0002 , B82Y10/00 , B82Y40/00
Abstract: 나노임프린트리소그라피공정용템플릿의제조방법이제공된다. 이방법은기판상에그 상부표면으로부터기판의표면으로내리막경사의적어도하나의측면을갖는양각제 1 증착막패턴을형성하는단계, 양각제 1 증착막패턴의내리막경사의적어도하나의측면을덮되, 양각제 1 증착막패턴의측면상부에서측면하부로갈수록폭이줄어드는형태를갖는제 2 증착막패턴을형성하는단계, 제 2 증착막패턴이형성된결과물의전면상에제 3 증착막을형성하는단계, 양각제 1 증착막패턴및 제 2 증착막패턴의상부표면들이동시에노출되도록제 3 증착막을평탄화하여, 양각제 1 증착막패턴과평탄화된제 3 증착막사이에개재된제 2 증착막나노패턴을형성하는단계, 평탄화된제 3 증착막을선택적으로식각하여음각마이크로패턴을형성하는단계, 및양각제 1 증착막패턴과평탄화된제 3 증착막사이에개재된제 2 증착막나노패턴을제거하여, 양각제 1 증착막패턴및 평탄화된제 3 증착막의상부표면들로부터기판의표면으로내리막경사의측면들에의해구성되는음각나노패턴을형성하는단계를포함한다.
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