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公开(公告)号：KR1019930003993B1
公开(公告)日：1993-05-19
申请号：KR1019890019313
申请日：1989-12-22
Applicant: 한국전자통신연구원
IPC: G06F13/14
Abstract: The method transmits data smoothly through data bus by monopolizing the bus only in memory consulting operation of a processor and the related memory. It comprises the three stages: in the 1st stage a processor drives a certain address on address bus during a certain period of a bus clock; in the 2nd stage the memory selected by the certain address stores the certain address during the certain bus clock; and in the 3rd stage when the process of storing is completed, the processor cancells the occupation of the address bus the make other processor use the address bus.
Abstract translation: 该方法仅在处理器和相关存储器的存储器咨询操作中通过垄断总线通过数据总线平滑地传输数据。 它包括三个阶段：在第一阶段，一个处理器在总线时钟的一定时间段内在地址总线上驱动某个地址; 在第二阶段，特定地址选择的存储器在特定的总线时钟存储特定地址; 并且在存储过程完成的第三阶段中，处理器取消对其他处理器使用地址总线的占用地址总线。
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公开(公告)号：KR1019920001812B1
公开(公告)日：1992-03-03
申请号：KR1019890019306
申请日：1989-12-22
Applicant: 한국전자통신연구원
Abstract: The method checks whether a transmission has been certainly carried out on a mutual basis. The method includes the steps of: transmitting address signals upon receipt of a data request from a processor (1); driving a data bus (4) for transferring a memory data from a memory (6); transmitting the selected data and sending an address responding signal through a status bus (5); and receiving a data responding signal through the status bus (5) from the processor (1) which has received the data.
Abstract translation: 该方法检查传输是否已经相互确定地进行。 该方法包括以下步骤：在从处理器（1）接收到数据请求时发送地址信号; 驱动用于从存储器（6）传送存储器数据的数据总线（4）; 发送所选择的数据并通过状态总线（5）发送地址响应信号; 以及从已经接收到该数据的处理器（1）通过状态总线（5）接收数据响应信号。
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