公开(公告)号：WO1997046944A1

公开(公告)日：1997-12-11

申请号：PCT/US1997001634

申请日：1997-02-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SINGH, Alok ,  ROY, Rajat ,  KUO, Jerry

IPC: G06F13/12

CPC classification number: G06F13/128

Abstract: An ethernet controller for controlling the transmission of data between a station and an ethernet having four FIFOs for managing the transmission of data between the station CPU, a memory buffer, and the ethernet. The four FIFOs each have a selected size to maximize performance of the controller. The controller includes a arbiter to arbitrate which pending request from each of the FIFOs will have priority. The controller limits the transmission of data by each FIFO to 32 bytes per grant. Each FIFO includes logic to convert data in a first bit size format to a second bit size format. The controller also includes logic to convert a 16 bit address to two 8 bit portions for transmission over an 8 bit address bus and logic to reformat the two 8 bit portions to the 16 bit address.

Abstract translation: 一个以太网控制器，用于控制站和具有四个FIFO的以太网之间的数据传输，用于管理站CPU，存储器缓冲区和以太网之间的数据传输。 四个FIFO都具有选定的大小以最大化控制器的性能。 控制器包括仲裁器，用于仲裁来自每个FIFO的待决请求将具有优先级。 控制器将每个FIFO的数据传输限制为每个授权32个字节。 每个FIFO包括将第一位大小格式的数据转换为第二位大小格式的逻辑。 控制器还包括将16位地址转换为两个8位部分以用于通过8位地址总线传输的逻辑，以及将两个8位部分重新格式化为16位地址的逻辑。

公开(公告)号：WO1997046932A1

公开(公告)日：1997-12-11

申请号：PCT/US1997000724

申请日：1997-01-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LEE, Sherman ,  KYLE, David, G.

IPC: G06F01/00

CPC classification number: H04L29/06 ,  G06F21/31 ,  G06F21/57 ,  G06F21/629 ,  H04L63/0428 ,  H04L63/08

Abstract: A computer overall system (100) includes client systems (102, 104, 106) which are centered around customer computers. Client systems are connectable through a communications network (114) with server systems (122, 124, 126) by way of a LAN (108, 116): wan (110, 118); or POTS (112, 120). Communications network (114) can be any type of interconnect which is connected to respective server system. A computer which is part of a client system or a server system, includes therein a microprocessor that is programmed by the manufacturer with various items of information regarding the microprocessor itself. This programmed information defines a predetermined capability for the computer where its predetermined capability is defined by a set of parameters maintained within the computer system including several parameters such as the maximum core frequency (i.e. which is a measure of the speed or how many megahertz the central processing unit of the microprocessor is capable of running at), the maximum instruction set, a description of all the features available from the microprocessor, and other information related to the maximum capabilities of the microprocessor and the system it can operate, as appropriate for the specific application, for example, microprocessor may have parameters which broadly or narrowly defined the client system or the server system of which the microprocessor is a part. The microprocessor could also be provided with a hard coded electronic encryption key. Similarly, as is also known to those skilled in the art, the microprocessor could be configurable by changing internal software to change the core frequency or to modify yet other features.

Abstract translation: 计算机总体系统（100）包括以客户计算机为中心的客户端系统（102,104,106）。 客户端系统可以通过LAN（108,116）与服务器系统（122,124,126）通过通信网络（114）连接。 或POTS（112,120）。 通信网络（114）可以是连接到相应服务器系统的任何类型的互连。 作为客户端系统或服务器系统的一部分的计算机在其中包括由制造商对由微处理器本身提供的各种信息项目编程的微处理器。 该编程信息为计算机定义了预定能力，其中其预定能力由在计算机系统内维护的一组参数来定义，其包括若干参数，例如最大核心频率（即哪个是速度的测量或中心多少兆赫兹 微处理器的处理单元能够运行，最大指令集，可从微处理器获得的所有功能的描述，以及与微处理器及其可操作的系统的最大功能有关的其他信息，适用于 具体应用，例如，微处理器可以具有广泛地或狭义地定义客户端系统或微处理器作为其一部分的服务器系统的参数。 微处理器还可以设置有硬编码的电子加密密钥。 类似地，如本领域技术人员也是已知的，微处理器可以通过改变内部软件来改变核心频率或修改其他特征来配置。

公开(公告)号：WO1997041592A1

公开(公告)日：1997-11-06

申请号：PCT/US1996020485

申请日：1996-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  MICHAEL, Mark, W. ,  FULFORD, H., Jim ,  BRENNAN, William, S.

IPC: H01L21/316

CPC classification number: H01L21/76801 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low permittivity interlevel structure comprising a dielectric formed on the topography of a semiconductor substrate. The dielectric comprises a lower region proximal to the semiconductor substrate, an intermediate region comprised of an oxide into which fluorine is incorporated in an atomic concentration of approximately four to ten percent, and an upper region. A method of forming the dielectric structure includes forming a first interconnect level on a substrate. A first dielectric layer, preferably a CVD oxide, is formed on the topography defined by the first interconnect and the substrate. A second dielectric layer, having a dielectric constant lower than the first dielectric layer, is then formed on the first dielectric layer. A third dielectric layer is formed on the second dielectric layer. The second dielectric layer is preferably formed in a CVD chamber from a silane or TEOS source and a fluorinating material such as SiF4.

Abstract translation: 包括在半导体衬底的形貌上形成的电介质的低介电常数层间结构。 电介质包括靠近半导体衬底的下部区域，由以约4％至10％的原子浓度掺入氟的氧化物构成的中间区域和上部区域。 形成电介质结构的方法包括在衬底上形成第一互连电平。 在由第一互连和衬底限定的形貌上形成第一电介质层，优选CVD氧化物。 然后在第一介电层上形成具有低于第一介电层的介电常数的第二电介质层。 在第二电介质层上形成第三电介质层。 第二电介质层优选地由硅烷或TEOS源形成在CVD室中，并且氟化材料例如SiF 4。

公开(公告)号：WO1997039400A1

公开(公告)日：1997-10-23

申请号：PCT/US1997001517

申请日：1997-01-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KYLE, David, G. ,  LEE, Sherman

IPC: G06F01/00

CPC classification number: G06F11/24 ,  G06F11/006

Abstract: A microprocessor (12) with automatic and dynamic partname determination including performance number. The microprocessor includes circuitry (38) that measures a core clock frequency for the microprocessor (12) and circuitry (36) that determines a performance indication for the microprocessor (12) in response to the measured core clock frequency.

Abstract translation: 具有包括性能数量的自动和动态部件名称确定的微处理器（12）。 微处理器包括测量微处理器（12）的核心时钟频率的电路（38）和响应于测量的核心时钟频率确定微处理器（12）的性能指示的电路（36）。

公开(公告)号：WO1997037302A1

公开(公告)日：1997-10-09

申请号：PCT/US1997001050

申请日：1997-01-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GROSSMAN, Leonid ,  LEE, Sherman

IPC: G06F09/445

CPC classification number: G06F9/4416 ,  H04L67/1008

Abstract: A method for choosing a particular server on a network and performing a remote boot by a client, the network including a plurality of servers operating in accordance with a plurality of network operating systems, includes identifying (36) each of the plurality of servers by address and by type of operating system, and selecting (37) one of the identified servers by address and type for booting on the network. Identifying further includes sending a FIND frame (32) from the client to the network, and receiving a FOUND frame (34) from each of the plurality of servers. A remote program load protocol followed by the server according to the FOUND frame is determined. Additionally, choosing a particular server on a network and performing a remote boot by a client includes identifying each of a plurality of servers according to characteristics of a FOUND frame including a frequency characteristic, selecting one of the identified servers, and performing a remote program load by a boot ROM on a client through the selected one of the identified plurality of servers. Identifying further includes determining whether a destination address of the FOUND frame is repeated in a same order in a data portion of the FOUND frame, wherein when the destination address is repeated in a same order, a frequency characteristic of the FOUND frame is determined.

Abstract translation: 一种用于在网络上选择特定服务器并由客户端执行远程启动的方法，所述网络包括根据多个网络操作系统操作的多个服务器，所述方法包括通过地址来标识（36）所述多个服务器中的每一个服务器 并根据操作系统的类型，并通过地址和类型在网络上引导来选择（37）所识别的服务器之一。 识别还包括从客户端发送FIND帧（32）到网络，以及从多个服务器中的每一个接收FOUND帧（34）。 确定根据FOUND框架的服务器后面的远程程序加载协议。 另外，选择网络上的特定服务器并且由客户端执行远程引导包括根据包括频率特性的FOUND帧的特性来识别多个服务器中的每一个，选择所识别的服务器之一以及执行远程程序负载 通过所选择的一个所识别的多个服务器中的客户机上的引导ROM。 识别还包括确定在FOUND帧的数据部分中是否以相同的顺序重复FOUND帧的目的地地址，其中当以相同的顺序重复目的地地址时，确定FOUND帧的频率特性。

公开(公告)号：WO1997036331A1

公开(公告)日：1997-10-02

申请号：PCT/US1996016540

申请日：1996-10-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  NAYAK, Deepak, Kumar ,  HEILER, Felicia ,  RAKKHIT, Rajat

IPC: H01L29/78

CPC classification number: H01L29/6659 ,  H01L29/7836

Abstract: Submicron nLDD CMOS logic devices with improved current drive and reduced reverse short-channel effects having heavily doped As and lightly doped P nLDD region.

Abstract translation: 亚微米nLDD CMOS逻辑器件具有改进的电流驱动和减少的反向短沟道效应，具有重掺杂的As和轻掺杂的P nLDD区域。

公开(公告)号：WO1997036323A1

公开(公告)日：1997-10-02

申请号：PCT/US1996017242

申请日：1996-10-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  OMID-ZAHOOR, Farrokh

IPC: H01L21/762

CPC classification number: H01L21/76237

Abstract: Formation of parasitic edge transistors at upper edges of trenches formed on a substrate of an integrated circuit is suppressed by implanting dopants into trench regions of the IC substrate before the trenches are formed in the trench regions by reactive ion etching. The widths of the trenches formed in the trench regions are narrower than the widths of the doped regions of the trench regions. The doped regions of the trench regions are formed by first implanting dopants into the trench regions and then heat treating the implanted regions to activate the dopants and to diffuse the dopants laterally from the implanted regions.

Abstract translation: 通过在通过反应离子蚀刻在沟槽区域中形成沟槽之前，通过在IC衬底的沟槽区域中注入掺杂剂来抑制形成在集成电路的衬底上的沟槽的上边缘处的寄生边缘晶体管的形成。 形成在沟槽区域中的沟槽的宽度比沟槽区域的掺杂区域的宽度窄。 沟槽区域的掺杂区域通过首先将掺杂剂注入到沟槽区域中，然后热处理注入区域以激活掺杂剂并使掺杂剂从注入区域侧向扩散而形成。

公开(公告)号：WO1997035257A1

公开(公告)日：1997-09-25

申请号：PCT/US1997001091

申请日：1997-01-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LYNCH, Thomas, W.

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F9/3824 ,  G06F12/0848

Abstract: A data cache is provided which stores stack data within a stack memory separate from the cache line oriented storage used for non-cache data. Data may be pushed, popped, and accessed via an offset from the stack memory without generating main memory addresses. A load/store unit coupled to the data cache may be configured to perform the address generation associated with stack accesses in parallel with performing the access to the stack memory. If the corresponding data is not stored within the stack memory, then an access to the cache line oriented storage may be performed. Therefore, no time penalty may be assessed for missing the stack memory. A stack memory is contemplated for use with respect to subroutine parameter passing. The calling routine may perform multiple push commands to place parameters for use by the subroutine onto the stack. The subroutine may then access and modify the parameters upon the stack. Finally, the calling routine may perform multiple pop commands to remove the parameters from the stack.

Abstract translation: 提供了一种数据高速缓存，其将堆栈数据存储在与用于非高速缓存数据的高速缓存行定向的存储器分离的堆栈存储器中。 可以通过来自堆栈存储器的偏移来推送，弹出和访问数据，而不产生主存储器地址。 耦合到数据高速缓存的加载/存储单元可以被配置为与执行对栈存储器的访问并行地执行与堆栈访问相关联的地址生成。 如果对应的数据没有存储在堆栈存储器中，则可以执行对面向高速缓存线的存储的访问。 因此，无法评估丢失堆栈内存的时间损失。 堆栈存储器被设想用于子程序参数传递。 调用例程可以执行多个推送命令以将子程序使用的参数放置到堆栈上。 然后，子程序可以访问和修改堆栈上的参数。 最后，调用例程可以执行多个pop命令来从堆栈中删除参数。

公开(公告)号：WO1997035251A1

公开(公告)日：1997-09-25

申请号：PCT/US1997001065

申请日：1997-01-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ASGHAR, Saf ,  IRETON, Mark ,  BARTKOWIAK, John, G.

IPC: G06F09/38

CPC classification number: G06F9/3017 ,  G06F9/3879 ,  G06F9/3885 ,  H04Q2213/13036 ,  H04Q2213/1305 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13107 ,  H04Q2213/13199 ,  H04Q2213/13299 ,  H04Q2213/13389 ,  H04Q2213/13396

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. The X86 core and the DSP core are coupled to each other and communicate data and timing signals for synchronization purposes. Thus, the DSP core offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP core also operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSP cores. Thus the present invention is backwards compatible with existing software.

Abstract translation: 包括通用CPU组件（如X86内核）的CPU或微处理器，还包括DSP内核。 CPU还包括一个智能DSP功能解码器或预处理器，用于检查X86操作码序列，并确定DSP功能是否正在执行。 如果DSP功能解码器确定正在执行DSP功能，则DSP功能解码器将操作码转换或映射到提供给DSP内核的DSP宏指令。 DSP内核执行一个或多个DSP指令以响应于宏指令来实现所需的DSP功能。 DSP内核使用较少数量的指令实现或执行DSP功能，同时也减少了数量的时钟周期，从而提高了系统性能。 如果指令高速缓存或指令存储器中的X86操作码不表示或不旨在执行DSP类型功能，则将操作码提供给当前现有技术计算机系统中发生的X86内核。 X86内核和DSP内核相互耦合，并传送数据和定时信号以实现同步。 因此，DSP核心从X86内核卸载这些数学函数，从而提高系统性能。 DSP内核还与X86内核并行运行，提供了更多的性能优势。 因此，本发明的CPU比X86逻辑更有效地实现DSP功能，而不需要额外的X86操作码。 本发明还生成根据包括X86和DSP内核的本发明的仅在X86仅CPU或CPU上透明地操作的代码。 因此，本发明与现有软件向后兼容。

公开(公告)号：WO1997031363A1

公开(公告)日：1997-08-28

申请号：PCT/US1997002811

申请日：1997-02-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HEWITT, Larry

IPC: G10H07/02

CPC classification number: G10H7/004 ,  G10H7/02 ,  G10H2230/031 ,  G10H2240/275

Abstract: The PC audio circuit (10) described interfaces with and provides audio enhancement to a host personal computer of the type including a central processor, system memory and a system bus. The PC audio circuit (10) includes a digital signal processor (DSP) (16) for processing wavetable data and generating digital audio signals for a plurality of voices. The wavetable data is stored in the host computer's system memory and transferred in portions, as needed by the DSP (16) to a smaller, low-cost cache memory (22) included with the PC audio circuit (10). The DSP (16) processes several frames of data samples for an active voice before processing another voice. Processing in this manner alleviates concerns about the percentage use of system bus bandwidth and the maximum allowable system bus latency. These concerns are further alleviated by deriving frequency compensated wavetable data and storing it in system memory to be retrieved by the DSP (16) for generating digital audio signals having high frequency ratios. Digital audio signals generated for each active voice are accumulated in cache memory (22). When the digital audio signals for all active voices have been accumulated, the accumulated data is transmitted from the cache memory (22) to an external digital-to-analog converter. Since wavetable data is stored in system memory, the cache memory (22) is smaller and less expensive than the local memory in prior art PC audio circuits. Thus, the described PC audio circuit (10) has a lower overall cost.

Abstract translation: 描述的PC音频电路（10）与包括中央处理器，系统存储器和系统总线的主机个人计算机接口并提供音频增强。 PC音频电路（10）包括用于处理波形数据并产生多个语音的数字音频信号的数字信号处理器（DSP）（16）。 波形数据被存储在主计算机的系统存储器中，并且根据DSP（16）的需要，以包括在PC音频电路（10）中的较小的，低成本的高速缓冲存储器（22）的一部分传送。 在处理另一个声音之前，DSP（16）处理主动语音的多个数据采样帧。 以这种方式进行的处理减轻了对系统总线带宽的使用百分比和最大允许系统总线延迟的担忧。 通过导出频率补偿波形数据并将其存储在由DSP（16）检索以产生具有高频率的数字音频信号的系统存储器中，进一步减轻了这些问题。 为每个活动语音生成的数字音频信号被累积在高速缓存存储器（22）中。 当用于所有活动语音的数字音频信号已被累积时，累积的数据从高速缓冲存储器（22）发送到外部数模转换器。 由于波形数据存储在系统存储器中，高速缓冲存储器（22）比现有技术的PC音频电路中的本地存储器更小且更便宜。 因此，所描述的PC音频电路（10）具有较低的总成本。