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    PROCEDE D'ISOLATION DE MOTIFS FORMES DANS UN FILM MINCE EN MATERIAU SEMI-CONDUCTEUR OXYDABLE
    31.
    发明专利
    PROCEDE D'ISOLATION DE MOTIFS FORMES DANS UN FILM MINCE EN MATERIAU SEMI-CONDUCTEUR OXYDABLE 未知

    公开(公告)号：FR2879020A1

    公开(公告)日：2006-06-09

    申请号：FR0413061

    申请日：2004-12-08

    Applicant: COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： VINET MAUD ,  BARBE JEAN CHARLES ,  PREVITALI BERNARD ,  POIROUX THIERRY

    IPC: H01L21/31

    Abstract: Un procédé d'isolation de motifs (1a) formés dans un film mince en un premier matériau semi-conducteur oxydable, d'une épaisseur inférieure ou égale à 10nm comporte successivement :- la formation, sur le film mince d'un masque définissant, dans le film mince, des zones libres et des zones recouvertes par le masque destinées à former sensiblement les motifs (1a),- une étape de formation sélective, au niveau des zones libres du film mince, d'une couche supplémentaire constituée par un oxyde d'un second matériau semi-conducteur,- l'oxydation des zones libres du film mince- et le retrait du masque de manière à libérer le film mince structuré sous forme de motifs (1 a) isolés par des zones oxydées (1 b).Les premier et second matériaux semi-conducteurs peuvent être identiques et l'étape de formation de la couche supplémentaire peut être réalisée par croissance par épitaxie sélective des zones libres du film mince.

    CMOS logic cell characterizing method for accelerating simulation of temporal dependence of delays effect in design of CMOS logic cells
    32.
    发明专利
    CMOS logic cell characterizing method for accelerating simulation of temporal dependence of delays effect in design of CMOS logic cells 未知

    公开(公告)号：FR2845180A1

    公开(公告)日：2004-04-02

    申请号：FR0212022

    申请日：2002-09-27

    Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： POIROUX THIERRY ,  FLATRESSE PHILIPPE

    IPC: G06F17/50 ,  H01L21/8238

    Abstract: The method comprises the modelling of a CMOS logic cell and the phase of determining the internal potentials of the cell based on a functional simulation of the modelled cell by utilizing a simulation signal (ST) which is a periodic binary signal. The determining phase includes the injection of a charge into the floating substrate (B) of each transistor of the cell, where the charge is proportional to the variation of internal potential of the transistor determined in the course of a predetermined temporal interval (TC) of the simulation signal preceding the instant of injection and exempt of injection, in a manner to accelerate the charging or discharging of the floating substrate (B) of the transistor. The injection current corresponds to the injected charge so that after the injection the variation of internal potential (Vb) of the transistor attains a value n times the measured variation of internal potential. The value of n is determined on the basis of measuring the variation of internal potential in the course of a cycle of the simulation signal and an estimated amplitude of the variation of the internal potential of the transistor between its states of static equilibrium (DC) and dynamic equilibrium (AC, steady state). The value of a coefficient of proportionality (A) is determined on the basis of the measuring of the variation of the internal potential and the variation of charge of the transistor in the course of a cycle of the simulation signal and the duration of injection. The simulation signal (ST) comprises in each period a transition separating two levels, corresponding to 0 and 1, and the instant of injection is situated on a level and at a distance from the transition. The duration of current injection is greater than the temporal step of functional simulation and lesser than the duration of a level. The two instants of consecutive injection are separated by a duration equal to two periods of the simulation signal, or by one period in a variant of the method, and the temporal interval (TC) has a duration equal to a period of the simulation signal. The initial instant of the temporal interval precedes the instant of injection by 1.5 periods of the simulation signal, and the final instant precedes the injection instant by 0.5 period of the simulation signal, and the final instant precedes the instant of injection by 0.5 period fo the simulation signal. In the functional simulation each transistor is replaced by a model of the transistor associated with three modelled sources of voltage controlled by voltage, allowing to determine a target internal potential (Vbc) to be attained after injection, and a modelled current source delivering the injection current proportional to a difference between the target potential and the internal potential at the instant of inejction. The evolution of internal potentials of the transistors is determined from the state of static equilibrium to the state of dynamic equilibrium relative to rising and falling transitions of the simulation signal and for two initial values of the simulation signal, and the internal potentials corresponding to the best and worst cases of temporal delay are deduced. A device (claimed) for characterizing a CMOS logic cell implements the method (claimed) and comprises modelling means and processing means.

    PROCEDE DE FABRICATION D'UN TRANSISTOR MOS A CANAL CONTRAINT
    36.
    发明专利
    PROCEDE DE FABRICATION D'UN TRANSISTOR MOS A CANAL CONTRAINT 未知

    公开(公告)号：FR2964787A1

    公开(公告)日：2012-03-16

    申请号：FR1057253

    申请日：2010-09-13

    Applicant: ST MICROELECTRONICS GRENOBLE 2 ,  COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： MORAND YVES ,  POIROUX THIERRY ,  BARBE JEAN-CHARLES

    IPC: H01L21/336

    Abstract: L'invention concerne un procédé de fabrication d'un transistor MOS (M) à canal contraint, comprenant les étapes suivantes : (a) former, en surface d'un substrat semiconducteur (10), un transistor MOS comprenant des régions de source et de drain et une grille sacrificielle isolée qui s'étend en partie sur des zones d'isolement (22) entourant le transistor ; (b) former une couche de matériau diélectrique dont la surface supérieure affleure la surface supérieure de la grille sacrificielle ; (c) éliminer la grille sacrificielle ; (d) graver au moins une partie supérieure des zones d'isolement découvertes pour y former des tranchées ; (e) remplir les tranchées d'un matériau (24) adapté à appliquer une contrainte au substrat ; et (f) former, dans l'espace laissé libre par la grille sacrificielle, une grille isolée (12) de transistor MOS.

    37.
    发明专利
    未知

    公开(公告)号：FR2911004B1

    公开(公告)日：2009-05-15

    申请号：FR0656010

    申请日：2006-12-28

    Applicant: COMMISSARIAT ENERGIE ATOMIQUE

    Inventor： VINET MAUD ,  THOMAS OLIVIER ,  ROZEAU OLIVIER ,  POIROUX THIERRY

    IPC: H01L21/336 ,  H01L21/8244 ,  H01L27/11

    Abstract: The method involves forming structures (150) on a substrate (100), where the structure includes primary semiconductor blocks (110a) forming a primary grid from a double grid of a fin FET transistor, and secondary semiconductor blocks (120a) forming a secondary grid from the double grid of the transistors. The blocks are situated at two sides of a semi-conductor zone (115a), and are separated from the semiconductor zone by two dielectric zones (109a, 119a) of the grids. The semiconductor zone of the secondary block is doped using selective implantation of the primary block of the structure. An independent claim is also included for a microelectronic device e.g. static RAM cell, comprising a finest transistor.

    39.
    发明专利
    未知

    公开(公告)号：FR2886761B1

    公开(公告)日：2008-05-02

    申请号：FR0505700

    申请日：2005-06-06

    Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

    Inventor： MORAND YVES ,  POIROUX THIERRY ,  VINET MAUD

    IPC: H01L21/8238

    Abstract: Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone.

    40.
    发明专利
    未知

    公开(公告)号：FR2886763B1

    公开(公告)日：2007-08-03

    申请号：FR0505701

    申请日：2005-06-06

    Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

    Inventor： MORAND YVES ,  POIROUX THIERRY ,  VINET MAUD

    Abstract: The method involves forming a stack by laminating an inner germanium silicon layer (3) between outer germanium silicon layers (2), in which the germanium concentration of the inner and outer germanium silicon layers are between 10 to 50 percent and between 0 to 10 percent, respectively. A silica layer (6) is formed on the surface of a main zone (5) by performing delineation and lateral thermal oxidation in the stack. Delineation process includes performing anisotropic plasma etching in the stack after deposition and photolithography of a photoresist. An independent claim is also included for: a germanium-based microelectronic component.

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