公开(公告)号：GB2411293A

公开(公告)日：2005-08-24

申请号：GB0510347

申请日：2003-10-16

Applicant: HRL LAB LLC ,  PROMTEK

Inventor： BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK JR WILLIAM M ,  YANG PAUL OU

IPC: H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L27/02 ,  H01L29/40

Abstract: A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and non functional conductive lines placed in the conductive layers. The non functional conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The non functional conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the non functional conductive lines.

公开(公告)号：AU4244000A

公开(公告)日：2000-11-10

申请号：AU4244000

申请日：2000-04-14

Applicant: HRL LAB LLC ,  HUGHES ELECTRONICS CORP

Inventor： BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/02 ,  H01L27/04 ,  H01L27/092

Abstract: A method and apparatus for protecting semiconductor integrated circuits from reverse engineering. Semiconductor active areas are formed on a substrate. A silicide layer is formed both over at least one active area of the semiconductor active areas and over a selected substrate area for interconnecting the at least one active area with another area through the silicide area formed on the selected substrate area. In a preferred embodiment a silicide layer formed on a first active area is interconnectingly merged laterally with a silicide layer formed on a second active area through the silicide layer formed on the selected substrate area.

公开(公告)号：GB2432971B

公开(公告)日：2007-11-07

申请号：GB0702704

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L27/02 ,  H01L23/58

公开(公告)号：GB2430800B

公开(公告)日：2007-06-27

申请号：GB0622262

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: H01L27/02 ,  H01L23/58

公开(公告)号：GB2412240B

公开(公告)日：2007-05-09

申请号：GB0512203

申请日：2005-06-15

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  BAUKUS JAMES P ,  HARBISON GAVIN J

IPC: H01L27/02 ,  H01L21/8238 ,  H01L29/76

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.

公开(公告)号：GB2403593A

公开(公告)日：2005-01-05

申请号：GB0309201

申请日：2001-05-11

Applicant: HRL LAB LLC

Inventor： CLARK JR WILLIAM M ,  BAUKUS JAMES P ,  CHOW LAP-WAI

IPC: H01L27/04 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088

Abstract: A camouflaged interconnection for interconnecting two spaced-apart implanted regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first implanted region forming a conducting channel between the two spaced-apart implanted regions, the conducting channel being of the same common conductivity type and bridging a region between the two spaced-apart regions, and a second implanted region of opposite conductivity to type, the second implanted region being disposed between the two spaced-apart implanted regions of common conductivity type and over lying the conducting channel to camouflage the conducting channel from reverse engineering.

公开(公告)号：AU2003293038A8

公开(公告)日：2004-06-18

申请号：AU2003293038

申请日：2003-11-20

Applicant: HRL LAB LLC ,  RAYTHEON CO

Inventor： CHOW LAP-WAI ,  BAUKUS JAMES P ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J

IPC: H01L23/58 ,  H01L27/02

Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

公开(公告)号：AU2003293038A1

公开(公告)日：2004-06-18

申请号：AU2003293038

申请日：2003-11-20

Applicant: HRL LAB LLC

Inventor： BAUKUS JAMES P ,  CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J

IPC: H01L23/58 ,  H01L27/02

Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

公开(公告)号：AU2003278917A1

公开(公告)日：2004-04-19

申请号：AU2003278917

申请日：2003-09-23

Applicant: HRL LAB LLC

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  HARBISON GAVIN J ,  BAUKUS JAMES P

IPC: G06K19/073 ,  H01L23/58 ,  G11C7/24 ,  H01L21/285

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.

公开(公告)号：AU2002316261A1

公开(公告)日：2003-01-02

申请号：AU2002316261

申请日：2002-06-13

Applicant: HRL LAB LLC

Inventor： CHOW LAP-WAI ,  CLARK WILLIAM M JR ,  BAUKUS JAMES P

IPC: H01L21/768 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/58 ,  H01L27/088