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公开(公告)号:DE69333604T2
公开(公告)日:2005-09-15
申请号:DE69333604
申请日:1993-02-01
Applicant: IBM
Inventor: JOSHI RAJIV V , CUOMO JEROME J , DALAL HORMAZDYAR M , HSU LOUIS L
IPC: H01L21/28 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532 , H01L23/485 , H01L21/60
Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.
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公开(公告)号:DE69329663D1
公开(公告)日:2000-12-21
申请号:DE69329663
申请日:1993-02-01
Applicant: IBM
Inventor: JOSHI RAJIV V , CUOMO JEROME J , DALAL HORMAZDYAR M , HSU LOUIS L
IPC: H01L21/28 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532 , H01L23/485 , H01L21/60
Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.
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33.
公开(公告)号:SG70045A1
公开(公告)日:2000-01-25
申请号:SG1997004072
申请日:1993-02-01
Applicant: IBM
Inventor: JOSHI RAJIV V , CUOMO JEROME J , DALAL HORMAZDYAR M , HSU LOUIS L
IPC: H01L21/28 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532 , H01L23/485 , H01L21/60 , H01L29/43 , H01L29/440 , H01L29/460 , H01L21/44 , H01L21/48 , H01L29/40
Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.
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公开(公告)号:DE69307274T2
公开(公告)日:1997-07-17
申请号:DE69307274
申请日:1993-10-05
Applicant: IBM
Inventor: BUTI TAQI N , JOSHI RAJIV V , SHEPARD JOSEPH F , HSU LOUIS LU-CHEN
IPC: H01L21/3205 , H01L21/74 , H01L21/762 , H01L21/768 , H01L21/822 , H01L21/98 , H01L23/522 , H01L27/04 , H01L23/535
Abstract: A wafer structure (10) suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate (20) having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads (24) of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads (22) of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps (28) of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate (30) having an oxide layer (32) thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.
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公开(公告)号:DE68917494D1
公开(公告)日:1994-09-22
申请号:DE68917494
申请日:1989-02-03
Applicant: IBM
Inventor: JOSHI RAJIV V
IPC: C23C16/04 , C23C16/14 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/768 , H01L29/43 , H01L29/78 , H01L21/90 , H01L29/76
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公开(公告)号:CA1308496C
公开(公告)日:1992-10-06
申请号:CA580787
申请日:1988-10-20
Applicant: IBM
Inventor: JOSHI RAJIV V
IPC: C23C16/04 , C23C16/14 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/768 , H01L29/43 , H01L29/78 , H01L29/76
Abstract: YO9-87-091 DEPOSITION OF TUNGSTEN ON SILICON IN NON-SELF-LIMITING CVD PROCESS A method of depositing tungsten on a substrate utilizing silicon reduction wherein the process is non-limiting as to the thickness of silicon that may be converted to tungsten. A silicon substrate is provided with at least one area of silicon material having a predetermined thickness and the substrate is exposed to a tungsten hexafluoride gas flow in a chemical vapor deposition environment. By adjusting the WF6 gas flow rate and the CVD process parameters, such as pressure, temperature and deposition time, the thickness of silicon converted to tungsten can be adjusted in order to convert the entire thickness. A novel structure having a midgap tungsten gate and tungsten source and drain metallized layers is also disclosed.
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