公开(公告)号：JP2000222898A

公开(公告)日：2000-08-11

申请号：JP36513699

申请日：1999-12-22

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To increase yield of chips while preventing signal contention of a sense amplifier using a high replacement flexibility redundancy and method. SOLUTION: Redundancy elements are integrated in at least two memory arrays which don't share the sense amplifiers. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block which does not share sense amplifiers with the first block. The corresponding row/column line is replaced to mimic the redundancy replacement of the first block.

公开(公告)号：JPH11317073A

公开(公告)日：1999-11-16

申请号：JP1817499

申请日：1999-01-27

Applicant: IBM

Inventor： JI BRIAN L ,  KIRIHATA TOSHIAKI

IPC: G11C11/407 ,  G11C8/10 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To provide a random access memory in which current scattering, voltage drops and heat generation related to the access of blocks in first and second storage units of a double memory unit are stabilized. SOLUTION: The memory is arranged between first and second storage units 220 and 222 and include a row selection unit 224 which conducts accesses to the storage places of the units 220 and 222 in accordance with first and second selection signals that are transmitted from the external side end section of the double memory unit to the selected row places. Different numbers are assigned to the blocks located at the distances corresponding from the external side end section so that the sum of the lengths of the propagation of the first and the second selection signals to the numbered blocks is maintained in a relatively constant manner regardless of the block number selected for the access.

公开(公告)号：JPH11283365A

公开(公告)日：1999-10-15

申请号：JP35791798

申请日：1998-12-16

Applicant: SIEMENS AG ,  IBM

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C11/401 ,  G11C7/18 ,  G11C8/14 ,  G11C16/06

Abstract: PROBLEM TO BE SOLVED: To constitute a hierarchical bit line architecture and a word line architecture by providing plural local bit line pairs in respective rows to be connected to memory cells and connecting them to master bit lines. SOLUTION: A bit line architecture 20 has plural local bit lines and plural master bit line pairs in respective rows Cj of a memory array. Respective contacts 29 of via holes are connected to drains or sources of FET switches 27 which are connected to the local bit lines. Switching states of the respective switches 27 are controlled by corresponding control lines 28 prolonging in a column direction. Respective control lines 28 are connected to all switches 27 provided parallel in the column direction. True master bit lines MBLj are selectively connected to true local bit lines LBLj via the switches 27it . On the other hand, the MBLj are selectively connected to complementary local bit lines LBLi via switches 27ic .

公开(公告)号：JPH10275498A

公开(公告)日：1998-10-13

申请号：JP7690198

申请日：1998-03-25

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI

IPC: G11C29/04 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide fault tolerant design appliable to a memory in any size by using a redundant unit(RU) containing the prescribed number of redundant element(RE). SOLUTION: A relevant RWLE is made active by the redundant coincidence detection phase of RU control circuit, a WLDIS signal is switched to '0' and an alternative line for selecting any RE in the RU is selected by a redundant word decoder (RWLDEC). Parallelly with this operation, the relevant RWLDEC gets address information and switches a correspondent output NR to '1'. The RWLDEC is provided with a variable size decoder and based on the number of address bits to be used for the RWLDEC, the bit required for decoding the suitable number of RE in the correspondent RU is set. Then, any redundant word line(RWL) is selected by the NR in the RWLDRV and the decoded result of RWLE.

公开(公告)号：JP2012178587A

公开(公告)日：2012-09-13

申请号：JP2012099631

申请日：2012-04-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GREGORY J FREDEMAN ,  KIRIHATA TOSHIAKI ,  ALAN J LESLIE ,  JOHN M SAFRAN

IPC: H01L21/82 ,  G11C16/04 ,  G11C17/14 ,  H01L27/10

CPC classification number: G11C17/16 ,  G11C17/165 ,  G11C29/027

Abstract: PROBLEM TO BE SOLVED: To provide a random access electrically programmable-e-fuse ROM.SOLUTION: A one-time programmable read-only memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled silicide migratable e-fuses. Word line selection is performed by decoding logic operating at Vwhile a bit line drive is switched between Vand a higher voltage Vfor programming. The OTPROM is thus compatible with and can be integrated with other technologies without adding costs and supports optimization of a high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improving sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.

Abstract translation: 要解决的问题：提供一种随机存取电可编程电子熔丝ROM。 解决方案：一次性可编程只读存储器（OTPROM）以二维阵列的大规模硅化物可迁移电子保险丝实现。 通过在V DD 下操作的解码逻辑执行字线选择，同时在V DD 之间切换位线驱动器， V P 进行编程。 因此，OTPROM与其他技术兼容并可与其他技术集成，而不增加成本，并支持在熔丝编程期间最小化电压路径的优化。 具有可编程参考的差分读出放大器用于改善感测余量，并且可以支持整个位线，而不是为各个保险丝提供感测放大器。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2003007839A

公开(公告)日：2003-01-10

申请号：JP2002110437

申请日：2002-04-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： KIRIHATA TOSHIAKI ,  SANG FUU DONG

IPC: H01L27/04 ,  H01L21/822 ,  H01L23/50 ,  H01L23/525 ,  H01L23/58 ,  H01L23/62 ,  H02M3/155

CPC classification number: H01L23/62 ,  H01L23/5256 ,  H01L23/58 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/30107 ,  H02M3/155 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a voltage generator that generates voltage, which is higher than voltage obtained on a chip from a chip power source, on an integrated circuit chip.
SOLUTION: A voltage generator 26 for the integrated circuit chip comprises an integrated circuit chip 20, which has a power source having voltage that can be used for the integrated circuit chip, an inductor that is on the integrated circuit chip electrically connected to the power source or contacts the integrated circuit chip, and flows electric current, and a clock that is constituted to turn on and off the electric current flowing from the power source via the inductor in a desired time interval to generate voltage spike larger than the voltage of the power source. The inductor is made of a part of lead frames 24 connecting the integrated circuit chip to an integrated circuit chip package 22.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种电压发生器，该电压发生器产生高于集成电路芯片上的来自芯片电源的芯片上获得的电压的电压。 解决方案：用于集成电路芯片的电压发生器26包括集成电路芯片20，其集成电路芯片20具有电源，该电源具有可用于集成电路芯片的电压，电感器位于与电源电连接的集成电路芯片上 或者与集成电路芯片接触并流动电流，以及构成为以期望的时间间隔通过电感器接通和断开从电源流过的电流的时钟，以产生大于功率的电压的电压尖峰 资源。 电感器由将集成电路芯片连接到集成电路芯片封装22的引线框架24的一部分制成。

公开(公告)号：JP2002334580A

公开(公告)日：2002-11-22

申请号：JP2002121334

申请日：2002-04-23

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  DHONG SANG HOO ,  OH HWA-JOON ,  WORDEMAN MATTHEW

IPC: G11C11/41 ,  G06F12/08 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To provide a method for controlling operation of a dynamic random access memory(DRAM) system having a plurality of memory cells constituted of rows and columns. SOLUTION: This method comprises a step in which a destructive read mode is enabled, the destructive read mode is a mode for read out destructively a bit of information stored in a DRAM memory cell being addressed. A bit in which information is read destructively is stored temporarily in a temporary storage device. A delay write.back.mode is enabled, this delay write-back-mode is a mode for restore bit of information in the DRAM memory cell being addressed afterward. Then, execution of the delay write-back-mode is scheduled in accordance with availability of space in the temporary storage device.

公开(公告)号：JP2002334579A

公开(公告)日：2002-11-22

申请号：JP2002104679

申请日：2002-04-08

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  DHONG SANG H ,  OH HWA-JOON

IPC: G11C11/409 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076

Abstract: PROBLEM TO BE SOLVED: To provide a method for improving write time for a dynamic random access memory(DRAM) having destructive read architecture. SOLUTION: This method is a method for prepairing dynamic random access memory(DRAM) cells for write operation having a condition previously set. This method comprises that a voltage level previously set in a cell is made before delay-rewriting in destructive read architecture, and this voltage level previously set has a value between a logic 0 voltage level and a logic 1 voltage level. The logic 0 voltage level corresponds to a first cell voltage value when 0 bit is stored in a cell, the logic 1 voltage level corresponds to a second cell voltage value when 1 bit is stored in a cell. Before a voltage level previously set is made in a cell, the cell has an initial voltage value corresponding to either of the logic 0 voltage level or the logic 1 voltage level.

公开(公告)号：JP2000036200A

公开(公告)日：2000-02-02

申请号：JP15147199

申请日：1999-05-31

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  CHRISTOPHER DOUGLAS WEAIT

IPC: G11C11/401 ,  G01R31/28 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  G11C29/00 ,  G06F11/22 ,  G06F12/06 ,  G06F12/16

Abstract: PROBLEM TO BE SOLVED: To improve the performance of an integrated circuit chip by setting the chip to obtain its optimum performance every time the power of the chip is increased and supplying the setting to a chip control. SOLUTION: During a self test, a condition is applied to a DRAM core 102 by an SPBIST logic 104, a control signal 110 is given to a control logic 108 and control parameters are modified. Then, by incremeting the signal 110, an internal timing control reduces an SA timing and a faster access/time is achieved. Then, similar tests are repeated by a faster SA timing and the logic 104 increments the signal 110 whenever a predicted result is obtained. These tests are repeated until the tests are failed and the limit of the SAT timing is exceeded. Then, the last value of the signal 110, at which the test is satisfied, i.e., the optimum value of the chip is stored in an NVRAM 106.

公开(公告)号：JPH11163299A

公开(公告)日：1999-06-18

申请号：JP27395598

申请日：1998-09-28

Applicant: SIEMENS AG ,  IBM

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HOENIGSCHMID HEINZ

IPC: H01L27/108 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide an improved architecture, in which an area penalty is reduced or there is substantially no area penalty in a high-density memory, using a diagonal bit line. SOLUTION: This semiconductor memory has a plurality of diagonal bit lines, having changes in the horizontal direction along a memory cell array 12 for facilitating the access to memory cells and being arranged in a pattern shape and a plurality of dual word lines which are not crossed at right angles with the bit lines, the dual word lines contain a master word line 22 in a first layer and a plurality of local word lines in a second layer, and the local word lines are solved by connection to the master word line 22 in a common line via electrical connections disposed at a plurality of intervals.