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    FAULT TOLERANT LOGICAL CIRCUITRY
    32.
    发明专利
    FAULT TOLERANT LOGICAL CIRCUITRY 未知

    公开(公告)号：CA1278349C

    公开(公告)日：1990-12-27

    申请号：CA561205

    申请日：1988-03-11

    Applicant: IBM

    Inventor： MALEY GERALD A ,  MOSLEY JOSEPH M ,  WEITZEL STEPHEN D

    IPC: H03K19/003 ,  H03K19/00 ,  H03K19/007

    Abstract: FAULT TOLERANT LOGICAL CIRCUITRY A fault tolerant logic circuit capable of absorbing many D.C. and A.C. defects. The logic circuit employs a number of redundant logic gate circuits. The gate circuits are arranged in at least first and second interconnected signal paths. The logic gate circuits have two independent outputs. The two independent outputs are each connected to an input in a discrete one of the first and second interconnected signal paths.

    ERROR DETECTION AND CORRECTION SYSTEM
    34.
    发明专利
    ERROR DETECTION AND CORRECTION SYSTEM 未知

    公开(公告)号：CA942427A

    公开(公告)日：1974-02-19

    申请号：CA127433

    申请日：1971-11-12

    Applicant: IBM

    Inventor： BOSSEN DOUGLAS C ,  HENLE ROBERT A ,  HSIAO MU Y ,  PRICER W DAVID ,  MALEY GERALD A

    IPC: G06F11/10 ,  G11C29/00

    Abstract: Errors in parallel binary data produced by a plurality of data track, e.g., a plurality of parallel shift registers, are corrected by a system in which the shift registers which are stuck, i.e., inalterable, are determined and counted. By single Hamming error detection means, the presence of a Hamming error and an indication of the bit position of a single Hamming error is made. Comparison means determine if the indicated Hamming error is coincident with a stuck track. Then, dependent on the parity condition of the data as well as the count of stuck tracks, apparatus is provided for complementing one or more of the stuck tracks and/or correcting the indicated Hamming error.

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