公开(公告)号：JP2000090683A

公开(公告)日：2000-03-31

申请号：JP25854198

申请日：1998-09-11

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  TANAKA MASAHIRO ,  MORI YOTARO

IPC: G11C11/41 ,  G11C7/06 ,  G11C11/419 ,  G11C16/06 ,  H03K3/356

Abstract: PROBLEM TO BE SOLVED: To provide a sense amplifier circuit in which a micro potential difference can be detected and amplified at high speed with low power consumption and the results can be retained. SOLUTION: Inverter pairs (TP0, TN0, TP1, TN1) are constituted by interconnecting the output of one inverter and the input of the other inverter. Drain of sense transistors (TN2, TN3) is connected in series with the source terminal of each inverter and differential input signal lines 12, 14 are connected with the gate of both sense transistors (TN2, TN3). Source of the sense transistors (TN2, TN3) is connected, as common node, with a transistor TN 4 functioning as a constant current source and an operating switch thus constituting a sense amplifier circuit 10.

公开(公告)号：JPH09213075A

公开(公告)日：1997-08-15

申请号：JP1893096

申请日：1996-02-05

Applicant: IBM

Inventor： YAMAZAKI NORITOSHI ,  MIYATAKE HISATADA

IPC: G11C11/413 ,  G11C7/10 ,  G11C8/04 ,  G11C11/408

Abstract: PROBLEM TO BE SOLVED: To enhance the data transfer rate by adding output signals indicating a carry and a borrow to a pre-decorder and supplying, these signals to a decoder to fetch two data stored in consecutive addresses in one cycle. SOLUTION: When a line 21 is selected by a pre-decoder device 13, lines 25-28 connected to junction points 101, 102 are brought into conduction by the selection of the line 21. Lines 25, 28 among these lines are connect to an INCN, however, since the INCN is a low order when an INC is a high order, they are interrupted at junction points 111, 119. Besides, the line 26 is connected to a BY0 via a junction point 120. Consequently, a first output becomes the BY0 according to an input address. As to the line 27, the junction point 114 with the INC is in a conductive state because the INC is of the high order. Consequently, the line 27 is connected to a BY1 (input address +1) via junction points 114, 121. Thus, the pre-decoder 13 outputs the address in accordance with the input address and addresses of the input address + one address simultaneously by one input address.

公开(公告)号：JP2005166170A

公开(公告)日：2005-06-23

申请号：JP2003403983

申请日：2003-12-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MIYATAKE HISATADA ,  SUNANAGA TOSHIO

IPC: G11C11/15 ,  G11C11/00 ,  G11C11/16

CPC classification number: G11C11/16 ,  G11C7/062 ,  G11C14/0081

Abstract: PROBLEM TO BE SOLVED: To provide an MRAM having a sense amplifier in which hardly any sense current flows into an MTJ element and hardly any voltage is applied and a potential difference that appears on a bit line pair is amplified at a high speed.
SOLUTION: A sense amplifier 18 comprises cyclically connected CMOS inverters 20 and 22; a P channel MOS transistor TP1 which shuts off power supply during standby and N channel MOS transistors TN5 and TN6 which are used to initialize the outputs of the sense amplifier during standby. A ground terminal 204 of the inverter 20 is connected to a bit line BLT through a transistor TN3 of a bit switch 4 and a ground terminal 224 of the inverter 22 is connected to a bit line BLC through a transistor TN4 of the bit switch 4.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种具有读出放大器的MRAM，其中几乎没有任何感测电流流入MTJ元件，并且几乎不施加任何电压，并且出现在位线对上的电位差以高速放大 。 解决方案：读出放大器18包括循环连接的CMOS反相器20和22; 在备用期间切断电源的P沟道MOS晶体管TP1和用于在待机期间初始化读出放大器的输出的N沟道MOS晶体管TN5和TN6。 逆变器20的接地端子204通过位开关4的晶体管TN3连接到位线BLT，并且反相器22的接地端子224通过位开关4的晶体管TN4连接到位线BLC。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004127463A

公开(公告)日：2004-04-22

申请号：JP2002293309

申请日：2002-10-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MIYATAKE HISATADA ,  UMEZAKI HIROSHI ,  KITAMURA TSUNEJI ,  SUNANAGA TOSHIO ,  NODA HIROYOSHI ,  ASANO HIDEO

IPC: G11C11/15 ,  G11C29/02 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC classification number: G11C11/16 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5006

Abstract: PROBLEM TO BE SOLVED: To provide a method for determining an optimum write bit line current and an optimum write word line current in an MRAM.
SOLUTION: In an asteroid curve represented by a bit line magnetic field H
x generated by a write bit line current I
B and a word line magnetic field H
y generated by a write word line current I
W , manufacturing variations and a design margin are taken into consideration to assume an asteroid curve AC
out outside all memory cell asteroid curves (located with a hatched area of Figure). The write bit line current and write word line current are selected so as to minimize write electric power consumed by a write current obtained by totalizing the write bit line current and the write word line current or a bit line and a write word line. In addition, a write bit line current and a write word line current are selected so as to form a synthetic magnetic field on a curve between a point H1 and a point H2 on the asteroid curve AC
out in order to prevent multi-selection.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004088597A

公开(公告)日：2004-03-18

申请号：JP2002248936

申请日：2002-08-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SUNANAGA TOSHIO ,  MIYATAKE HISATADA ,  KITAMURA TSUNEJI

IPC: H01L21/82 ,  G06F15/78 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H03K19/173 ,  H03K19/177

CPC classification number: G06F15/7867

Abstract: PROBLEM TO BE SOLVED: To provide a field programmable gate array (FPGA) which can shorten a configuration time and a time for rewriting wiring information and logic arrangement information, and can reduce its occupation area.
SOLUTION: For storing FPGA wiring information, magnetic memory elements MTJ1 to MTJn are provided as MRAM memory cells. A shift register 71 is used to input the wiring information to the magnetic memory elements MTJ1 to MTJn. The register 71 includes register elements SR1 to SRn corresponding to the magnetic memory elements MTJ1 to MTJn. The wiring information are serially input to the register elements SR1 to SRn and stored therein. When the power is turned on, the wiring information of the magnetic memory elements MTJ1 to MTJn are latched by latch elements LT1 to LTn and output to a switch circuit 6 for interconnecting logic blocks.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003198354A

公开(公告)日：2003-07-11

申请号：JP2001382556

申请日：2001-12-17

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI

IPC: G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H03K19/00

Abstract: PROBLEM TO BE SOLVED: To retain a latch status in a logic circuit which is on stand by status without losing original features in the logic circuit which achieves low electric power consumption and high speed performance using a MTCMOS circuit. SOLUTION: Power source lines Vdd and Vss, and virtual power source lines v-Vdd and v-Vss are connected with MOSFETHvt-Tr1 and Hvt-Tr2 which have high threshold voltage. Power source is supplied from v-Vdd and v-Vss to the combinational logic circuit 1 and nonvolatile latch circuits NVL1 to n. NVL1 to n are connected to arbitrary nodes which require status report on the stand by status in the combinational logic circuit 1. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003157671A

公开(公告)日：2003-05-30

申请号：JP2001358222

申请日：2001-11-22

Applicant: IBM

Inventor： MIYATAKE HISATADA ,  SUNANAGA TOSHIO ,  KITAMURA TSUNEJI

IPC: G11C11/14 ,  G11C11/15 ,  H03K3/356

Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile latch circuit in which nonvolatile memory elements are individually arranged within a logic circuit. SOLUTION: Tunnel magneto resistive elements MTJ0 and MTJ1 are connected to the respective sources of inverters INV1 and INV2 having a C-MOS structure and output and input of the inverters INV1 and INV2 are mutually cross connected. Transistors Tr5 and Tr6 which are used for precharging are connected to the output of the inverters and a transistor Tr7 is arranged between the elements MTJ0 and MTJ1 and the ground. Data are written into the elements MTJ0 and MTJ1 by the current that is flowing in a data writing line DWL and the states recorded in the elements MTJ0 and MTJ1 are taken out to an output OUT and an output OUT bar by REFRESHN signals.

公开(公告)号：JP2003007080A

公开(公告)日：2003-01-10

申请号：JP2001185167

申请日：2001-06-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： SUNANAGA TOSHIO ,  MIYATAKE HISATADA ,  KITAMURA TSUNEJI ,  ASANO HIDEO

IPC: H01L27/04 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To reduce a test cost by omitting a shifting process in which a chip on a wafer is shifted from a test device to a cutting device once to cut a fuse of a fuse circuit block in a conventional fuse circuit block. SOLUTION: This device is provided with two non-volatile storage elements 16, 18 storing data of connection or cut off of a fuse circuit, a circuit changing the direction of magnetization of this non-volatile storage elements 16, 18, and a current mirror circuit reading data stored in the non-volatile storage elements 16, 18.

Abstract translation: 要解决的问题：通过省略将晶片上的芯片从测试装置切换到切割装置一次以切断常规熔丝电路块中的熔丝电路块的熔丝的移位处理来降低测试成本。 解决方案：该设备设有两个非易失性存储元件16,18，其存储熔丝电路的连接或切断数据，改变该非易失性存储元件16,18和电流镜18的磁化方向的电路 存储在非易失性存储元件16,18中的电路读取数据。

公开(公告)号：JP2003007068A

公开(公告)日：2003-01-10

申请号：JP2001191191

申请日：2001-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： MIYATAKE HISATADA

IPC: G11C11/412 ,  G11C15/04

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption of a static RAM by reducing variation of potentials of bit lines 21a, 21b of a true side or a complementary side in write of data in a memory cell 55.
SOLUTION: A memory cell 55 has inverters of a true side and a complementary side constituting a flip-flop. A ground side node 13 and a power source side 14 being common to them are provided at a ground side and a power source side of a true side and a complementary side. In write of data, a potential of the ground side node 13 is raised temporarily to a potential of the power source side node 14.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：通过在存储单元55中的数据写入中减小真实侧或互补侧的位线21a，21b的电位变化来降低静态RAM的功耗。解决方案：存储单元55具有逆变器 构成触发器的真实面和互补面。 在真面和互补侧的接地侧和电源侧设置有与它们共同的接地侧节点13和电源侧14。 在写入数据时，接地侧节点13的电位暂时升高到电源侧节点14的电位。

公开(公告)号：JP2002368197A

公开(公告)日：2002-12-20

申请号：JP2001163655

申请日：2001-05-31

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： KITAMURA TSUNEJI ,  SUNANAGA TOSHIO ,  MIYATAKE HISATADA ,  NAKAMURA TAKASHI

IPC: G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile magnetic memory cell and a storage circuit block employing the same. SOLUTION: A nonvolatile memory cell 32 includes a bit line 14; a storage element 10, including a ferromagnetic layer in which its magnetizing direction varies, depending on the direction of the magnetic field generated by a current flowing through the bit line 14; a conductor 12 for connecting the bit line 14 to the element 10, a switching element 28; a first wiring structure 24 sandwiching the element 10 between the conductors 12 and itself, and connecting the element 10 to one end of the element 28; a write work line 16 intersecting with the bit line 14 in a no-contact manner therewith; and an insulation film 20 for insulating the work line 16 from the element 10.

Abstract translation: 要解决的问题：提供一种非易失性磁性存储单元和使用其的存储电路块。 解决方案：非易失性存储单元32包括位线14; 存储元件10，其包括根据由流过位线14的电流产生的磁场的方向，其磁化方向变化的铁磁层; 用于将位线14连接到元件10的导体12，开关元件28; 将元件10夹在导体12和本身之间并将元件10连接到元件28的一端的第一布线结构24; 写入工作线16与位线14以不接触的方式相交; 以及用于将工作线16与元件10绝缘的绝缘膜20。