公开(公告)号：GB2530043A

公开(公告)日：2016-03-16

申请号：GB201415951

申请日：2014-09-10

Applicant: IBM

Inventor： BLAETTLER TOBIAS ,  MITTELHOLZER THOMAS ,  PAPANDREOU NIKOLAOS ,  PARNELL THOMAS ,  POZIDIS CHARALAMPOS ,  STANISAVLJEVIC MILOS

IPC: G11C13/00 ,  G06F11/10 ,  G06F12/02 ,  G11C11/56 ,  G11C16/34 ,  G11C29/26

Abstract: A device 10 and method for storing data in a plurality of multi-level cell (MLC) memory chips 21; each of the multi-level cell memory chips 21 comprising memory cells having a plurality of programmable levels. The device comprises a scrambling unit which generates a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored; a calculation unit which evaluates or calculates a cost function (efficiency metric) for each of the candidate scrambled sequences of data, the result of each of the cost functions being indicative of a balancing degree of sub-sequences of a candidate scrambled sequence, when the sub-sequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips; a selection unit which selects one of the candidate scrambled sequences of data based on the results of the calculated cost functions; and a storing unit which stores the selected candidate scrambled sequence of data in the plurality of multi-level cell memory chips by storing the sub-sequences of the selected candidate scrambled sequence across the plurality of multi-level memory chips. An encoding unit 6 may also be included to encode the selected scrambled sequence of data, before storing using an error correcting code (ECC). The scrambling operation may involve an XOR on the stored and scrambled data (figures 3 and 4) .

公开(公告)号：GB2527604A

公开(公告)日：2015-12-30

申请号：GB201411513

申请日：2014-06-27

Applicant: IBM

Inventor： MITTELHOLZER THOMAS ,  PAPANDREOU NIKOLAOS ,  PARNELL THOMAS ,  POZIDIS CHARALAMPOS

IPC: G11C11/56 ,  G06F11/10 ,  G11C13/00 ,  H03M13/00

Abstract: A method, apparatus (3,4 figures 1,10 and 11) and computer program implementation for encoding data for storage in multilevel (q-level) memory cells (2, figure 1) having q cell-levels. Input data words are encoded into respective codewords, each having N symbols with one of q symbol-values, via an encoding scheme adapted such that the q symbol-values have unequal multiplicities within at least some codewords (figure 3), and the multiplicity of each of the q symbol-values in every codeword is no less than p, where p is greater than or equal to two (2) and more preferably greater than or equal to three (3). A first type of encoding scheme uses recursive symbol-flipping to enforce the p-constraint, adding indicator symbols to indicate the flipped symbols. A second type of encoding scheme (figure 4) maps data words to codewords of a union of permutation codes, the initial vectors for these permutation codes being selected to enforce the p-constraint. The N q-ary symbols of each codeword are supplied for storage in respective cells of the multilevel memory 2. The multilevel memory cells may be flash or more preferably phase change memory cells. The apparatus and method is reported to improve the self adaptive detection techniques utilising estimate statistics in light of the effects of ageing and drifting of the memory cells.

公开(公告)号：DE112012000372B4

公开(公告)日：2015-05-21

申请号：DE112012000372

申请日：2012-02-24

Applicant: IBM

Inventor： PANTAZI ANGELIKI ,  SEBASTIAN ABU ,  PAPANDREOU NIKOLAOS ,  POZIDIS CHARALAMPOS ,  FREY URS

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/02

Abstract: Verfahren zum Programmieren einer Phasenwechselspeicherzelle (10), wobei das Verfahren aufweist: (a) Anlegen eines Vorspannungssignals (VBL) an die Zelle, wobei ein Messabschnitt (m) des Vorspannungssignals ein Profil hat, das mit der Zeit variiert; (b) Durchführen einer Messung (TM) abhängig davon, ob eine vorbestimmte Bedingung erfüllt ist, wobei diese Bedingung vom Zellstrom während des Messabschnitts des Vorspannungssignals abhängig ist; (c) Erzeugen eines Programmiersignals in Abhängigkeit von der Messung (TM); und (d) Anlegen des Programmiersignals, um die Zelle (10) zu programmieren.

公开(公告)号：GB2513749B

公开(公告)日：2014-12-31

申请号：GB201411882

申请日：2012-11-20

Applicant: IBM

Inventor： MITTELHOLZER THOMAS ,  PAPANDREOU NIKOLAOS ,  POZIDIS CHARALAMPOS

IPC: G06F11/10

公开(公告)号：GB2509858A

公开(公告)日：2014-07-16

申请号：GB201406675

申请日：2012-06-27

Applicant: IBM

Inventor： MITTELHOLZER THOMAS ,  PAPANDREOU NIKOLAOS ,  POZIDIS CHARALAMPOS

IPC: G11C11/56

Abstract: Methods and apparatus are provided for detecting N-symbol codewords stored in multilevel-cell solid-state memory. Each codeword is a permutation of an N-symbol vector of a predefined set of N-symbol vectors. The symbols of each codeword, each of which has one of q symbol values, are stored in respective q-level cells of solid state memory (2), where N≥q>2. The memory cells storing a group of codewords are read to obtain respective read signals each comprising N signal components corresponding to respective symbols of a codeword. The components of each read signal are ordered according to signal level to produce an ordered read signal. Corresponding components of the ordered read signals are averaged to produce an average read signal. A reference signal level corresponding to each of the q levels of the memory cells is determined in dependence on the average read signal and predefined probabilities of occurrence of each symbol value at each symbol position in a said codeword whose symbols are ordered according to symbol value. The codeword corresponding to each read signal is then detected in dependence on the reference signal levels.

公开(公告)号：GB2502553A

公开(公告)日：2013-12-04

申请号：GB201209594

申请日：2012-05-30

Applicant: IBM

Inventor： SEBASTIAN ABU ,  PAPANDREOU NIKOLAOS ,  POZIDIS CHARALAMPOS

IPC: G11C13/00 ,  G11C11/22

Abstract: Methods and apparatus are provided for read measurement of resistive memory cells 11 having two or more programmable cell-states. In a voltage-mode read operation, at least one initial voltage is applied 13 to each cell 11 and a measurement, indicative of cell current 14 due to the initial voltage, is made. A read voltage is then determined for the cell in dependence on the initial measurement. The read voltage is applied to the cell 11, and a read measurement, indicative of cell current 14 due to the read voltage, is made. A cell-state metric dependent on the read measurement is then output. For example, the read measurement may be output as a cell-state metric. The read voltages for cells are determined in such a manner that the cell-state metric exhibits a desired property, e.g. provides an enhanced programming window (figure 5,6) and/or a desired programming curve shape. A current-mode read operation, involving application of currents to cells 11 and measuring resulting voltages can be similarly performed.

公开(公告)号：DE112012000372T5

公开(公告)日：2013-10-17

申请号：DE112012000372

申请日：2012-02-24

Applicant: IBM

Inventor： PANTAZI ANGELIKI ,  SEBASTIAN ABU ,  PAPANDREOU NIKOLAOS ,  POZIDIS CHARALAMPOS ,  FREY URS

IPC: G11C16/10

Abstract: Es werden Verfahren und Vorrichtungen zum Programmieren einer Phasenwechselspeicherzelle (10) bereitgestellt. Ein Vorspannungssignal (VBL) wird an die Zelle angelegt. Ein Messabschnitt (m) des Vorspannungssignals hat ein Profil, das mit der Zeit variiert. Eine Messung (TM), die von der Erfüllung einer vorbestimmten Bedingung abhängig ist, wird dann durchgeführt. Die vorbestimmte Bedingung ist vom Zellstrom während des Messabschnitts (m) des Vorspannungssignals abhängig. Ein Programmiersignal wird in Abhängigkeit von der Messung (TM) erzeugt, und das Programmiersignal wird angelegt, um die Zelle (10) zu programmieren.

公开(公告)号：GB2496822B

公开(公告)日：2013-10-02

申请号：GB201304453

申请日：2011-08-26

Applicant: IBM

Inventor： ELEFTHERIOU EVANGELOS ,  PANTAZI ANGELIKI ,  PAPANDREOU NIKOLAOS ,  POZIDIS CHARALAMPOS ,  SEBASTIAN ABU

IPC: G11C13/00 ,  G11C11/56 ,  H01L45/00

公开(公告)号：GB2492701A

公开(公告)日：2013-01-09

申请号：GB201218792

申请日：2011-03-23

Applicant: IBM

Inventor： ELEFTHERIOU EVANGELOS ,  PANTAZI ANGELIKI ,  PAPANDREOU NIKOLAOS ,  POZIDIS CHARALAMPOS ,  SEBASTIAN ABU

IPC: G11C11/56 ,  G11C13/00

Abstract: A method is provided that comprises a step of programming the PCM cell to have a respective definite cell state by at least one current pulse flowing to the PCM cell, said respective definite cell state being defined at least by a respective definite resistance level, a step of controlling said respective current pulse by a respective bitline pulse and a respective wordline pulse, and a step of controlling said respective bitline pulse and said respective wordline pulse dependent on an actual resistance value of the PCM cell and a respective reference resistance value being defined for the definite resistance level.

公开(公告)号：DE112011100217T5

公开(公告)日：2012-10-31

申请号：DE112011100217

申请日：2011-03-23

Applicant: IBM

Inventor： ELEFTHERIOU EVANGELOS S ,  PAPANDREOU NIKOLAOS ,  POZIDIS CHARALAMPOS ,  SEBASTIAN ABU ,  PANTAZI ANGELIKI

IPC: G11C13/00

Abstract: Es wird ein Verfahren bereitgestellt, das einen Schritt des Programmierens der PCM-Zelle durch mindestens einen Strompuls, der der PCM-Zelle zufließt, umfasst, um einen jeweiligen bestimmten Zellzustand anzunehmen, wobei der jeweilige bestimmte Zellzustand durch mindestens eine jeweilige bestimmte Widerstandsstufe festgelegt ist, und das einen Schritt des Steuerns des jeweiligen Strompulses durch einen jeweiligen Bitleitungs- und einen jeweiligen Wortleitungspuls sowie einen Schritt des Steuerns des jeweiligen Bitleitungs- und des jeweiligen Wortleitungspulses in Abhängigkeit von dem momentanen Widerstandswert der PCM-Zelle und von einem jeweiligen Bezugs-Widerstandswert umfasst, der für die bestimmte Widerstandsstufe festgelegt ist.