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    INTEGRAL HIERARCHICAL BINARY STORAGE ELEMENT
    31.
    发明专利
    INTEGRAL HIERARCHICAL BINARY STORAGE ELEMENT 未知

    公开(公告)号：CA953032A

    公开(公告)日：1974-08-13

    申请号：CA130046

    申请日：1971-12-14

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM F ,  HO IRVING T ,  PRICER WILBUR D

    IPC: G06F12/08 ,  G11C11/415 ,  G11C19/00

    Abstract: A binary data storage system of a data processing system is comprised of electrically independent storage modules, each module comprised of a matrix of electrically independent storage devices, with each storage device being an integral circuit element comprised of a first matrix of binary storage cells and associated selection circuitry, and a second matrix of binary storage cells and associated selection circuitry. The design of the binary storage cell of the first matrix and associated selection circuitry is such that a large number of storage cells can occupy a unit space but provide relatively slow access to the binary data manifested by the cell. The second matrix of binary storage cells and associated selection circuitry is formed in such a way that a relatively small number of storage cells are provided with a relatively high speed of access to the binary data manifested in the storage cells. Each storage device has a single terminal for the transfer of a single binary bit to or from the storage device. Each of the previously mentioned storage modules also has a single terminal for the transfer of a single binary bit to or from the storage module. All of the terminals of the storage devices are connected in common to the terminal of a storage module. One storage module is provided for each binary bit of a data processing system binary data word to be transferred between the storage system and the central processing unit of the data processing system. The most recently accessed binary data will be manifested in the high speed storage cells of the second matrix such that when address information is sent to the storage system, a large percentage of the requests for access to the storage system will find the data in the high speed portion of each of the storage devices providing an effective access time to the data in the storage system significantly faster than if the access to the data were required to be made to the storage cells of the first matrix.

    BIPOLAR ECL INPUT CIRCUIT FOR CMOS DEVICES
    34.
    发明专利
    BIPOLAR ECL INPUT CIRCUIT FOR CMOS DEVICES 未知

    公开(公告)号：CA1285622C

    公开(公告)日：1991-07-02

    申请号：CA581536

    申请日：1988-10-27

    Applicant: IBM

    Inventor： PRICER WILBUR D ,  WIEDMAN FRANCIS W

    IPC: H03K5/02 ,  H03K19/0175 ,  H03K19/0944 ,  H03K19/094

    Abstract: An ECL input circuit which receives an ECL input signal and which generates, in response to the input signal, a CMOS-compatible output signal. The input circuit includes a bipolar transistor, having its emitter region adapted to receive the ECL input signal, having its collector region coupled to a first current source, and having its base region connected to a second current source. The circuit further includes an output circuit which is coupled to the collector region of the bipolar transistor for providing the CMOS-compatible signal.

    STORAGE SYSTEM HAVING BILATERAL FIELD EFFECT TRANSISTOR PERSONALIZATION
    35.
    发明专利
    STORAGE SYSTEM HAVING BILATERAL FIELD EFFECT TRANSISTOR PERSONALIZATION 未知

    公开(公告)号：CA1169556A

    公开(公告)日：1984-06-19

    申请号：CA368425

    申请日：1981-01-13

    Applicant: IBM

    Inventor： PRICER WILBUR D ,  SELLECK JAMES E

    IPC: G11C17/00 ,  G11C11/34 ,  G11C11/40 ,  G11C11/56 ,  G11C17/12 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/112 ,  H01L29/10

    Abstract: A Storage System Having Bilateral Field Effect Transistor Personalization A storage system, such as a read only memory, is provided which includes field effect transistors each having first and second spaced apart diffusion regions of a given conductivity and a gate electrode, with at least one of the two diffusion regions of selected transistors having a third diffusion adjacent to one of the first and second diffusion regions under the gate electrodes to provide a higher voltage threshold for the gate electrode to one diffusion than for the gate electrode to the other of the two diffusions. A voltage is applied to the first diffusion having a polarity and magnitude sufficient to neutralize or eliminate the effects of the higher threshold during a first time period and the current flowing between the first and second diffusions is sensed. During a second period of time the voltage is applied to the second diffusion and the current flow between the first and second diffusions is again sensed. In this manner two cells or bits of information are stored in each transistor, one at the first diffusion and one at the second diffusion. Multilevel storing may also be employed by establishing one of more than two predetermined voltage thresholds at each of the first and second diffusions. BU9-79-017

    36.
    发明专利
    未知

    公开(公告)号：FR2396386A1

    公开(公告)日：1979-01-26

    申请号：FR7818480

    申请日：1978-06-13

    Applicant: IBM

    Inventor： JOSHI L ,  PRICER WILBUR D

    IPC: G11C11/403 ,  G11C11/405 ,  G11C11/42 ,  G11C11/419 ,  G11C11/24 ,  G11C11/40

    Abstract: A memory is produced which has a series circuit including charge storage means, an impedance and switching means and an amplifier having an input connected to the series circuit at a point between the charge storage means and the impedance and an output coupled to a bit/sense line. The switching means is controlled by a pulse from a word line. The series circuit interconnects the bit/sense line and a point of reference potential. In a preferred embodiment, the switching means is a first field effect transistor having its gate electrode connected to the word line and the amplifier is a second field effect transistor having its gate electrode connected to the series circuit at a point between the charge storage means and the impedance and having one of its current carrying electrodes coupled to the bit/sense line and its other current carrying electrode coupled to a point of reference potential.

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