公开(公告)号：DE69637135T2

公开(公告)日：2008-02-21

申请号：DE69637135

申请日：1996-02-20

Applicant: IBM

Inventor： CHRISTENSEN KENNETH JUSSI ,  CHORPENNING JACK S ,  SIEGEL MICHAEL STEVEN ,  STAMMELY THOMAS E ,  STROLE NORMAN CLARK ,  WILSON KENNETH THOMAS ,  ZEISZ RAYMOND LOUIS JR

IPC: H04L12/24 ,  H04L12/433 ,  H04L5/14 ,  H04L12/28 ,  H04L12/40 ,  H04L12/44 ,  H04L12/46 ,  H04L29/06

Abstract: A station in a communications network determines the mode (full-duplex or half-duplex) in which it communicates with a concentrator port by establishing a Registration routine between the station and the concentrator port. The station and concentrator port exchange frames which disclose the capabilities of the concentrator port. If the concentrator port has duplex capabilities, the station enters as a duplex station. Otherwise, the station enters in a half-duplex (token ring) mode.

公开(公告)号：ES2265971T3

公开(公告)日：2007-03-01

申请号：ES00959158

申请日：2000-08-24

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  GALLO ANTHONY MATTEO ,  HEDDES MARCO C ,  RAO SRIDHAR ,  SIEGEL MICHAEL STEVEN

IPC: G06F13/00 ,  G06F15/16 ,  G06F13/38 ,  G06F13/40 ,  G06F15/00 ,  G06F15/173 ,  G06F15/177 ,  G06F15/76 ,  H04L12/56

Abstract: Aparato que comprende: un procesador del punto de control; un dispositivo de interfaz conectado operativamente a dicho procesador del punto de control por un camino de control y que proporciona un camino de datos de alta velocidad, teniendo dicho dispositivo de interfaz un substrato (10) de semiconductores; una pluralidad de procesadores (12) del interfaz formados sobre dicho substrato, siendo el número de dichos procesadores al menos cinco; una memoria interna de instrucciones formada sobre dicho substrato y que almacena instrucciones de manera accesible para dichos procesadores del interfaz; una memoria interna de datos formada sobre dicho substrato y que almacena datos que pasan a través de dicho dispositivo, de manera accesible para dichos procesadores del interfaz; y una pluralidad de puertos de entrada/salida formados sobre dicho substrato; conectando al menos uno de dichos puertos de entrada/salida a dicha memoria interna de datos con la memoria externa de datos; intercambiando, al menos otros dos de dichos puertos de entrada/salida, datos que pasan a través del dispositivo de interfaz, con una red externa a la velocidad del medio bajo la dirección de dichos procesadores del interfaz; cooperando dicho procesador del punto de control con dicho dispositivo de interfaz, cargando en el interior de dicha memoria de instrucciones las instrucciones que han de ser ejecutadas por dichos procesadores del interfaz al dirigir el intercambio de datos entre dichos puertos de entrada/salida de intercambio de datos y el flujo de datos a través de dicha memoria de datos.

公开(公告)号：HK1069046A1

公开(公告)日：2005-05-06

申请号：HK05102297

申请日：2005-03-15

Applicant: IBM

Inventor： ALLEN JAMES JR ,  BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  GAUR SANTOSH PRASAD ,  HEDDES MARCO C ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

IPC: G06F15/16 ,  G06F15/177 ,  H04L20060101 ,  H04J20060101 ,  H04L12/56 ,  H04Q20060101 ,  H04Q3/00 ,  H04Q3/545

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

公开(公告)号：PL355786A1

公开(公告)日：2004-05-17

申请号：PL35578600

申请日：2000-12-21

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  DAVID GORDON TAYLOR ,  GALLO ANTHONY MATTEO ,  HEDDES MARCO ,  JENKINS STEVEN KENNETH ,  LEAVENS ROSS BOYD ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

IPC: H04L12/28 ,  H04L12/46 ,  H04L12/56 ,  H04L45/60 ,  G06F9/46

Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.

公开(公告)号：CZ20021442A3

公开(公告)日：2002-07-17

申请号：CZ20021442

申请日：2000-12-21

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  DAVIS GORDON TAYLOR ,  GALLO ANTHONY MATTEO ,  HEDDES MARCO ,  JENKINS STEVEN KENNETH ,  LEAVENS ROSS BOYD ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

IPC: H04L12/28 ,  H04L12/46 ,  H04L12/56 ,  H04L45/60 ,  G06F9/46

Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.

公开(公告)号：AU4430901A

公开(公告)日：2001-10-30

申请号：AU4430901

申请日：2001-03-26

Applicant: IBM

Inventor： CALVIGNAC JEAN LOUIS ,  HEDDES MARCO ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

IPC: H04L12/54 ,  H04Q11/04 ,  G06F9/00

Abstract: A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.

公开(公告)号：CA2328268A1

公开(公告)日：2001-07-04

申请号：CA2328268

申请日：2000-12-12

Applicant: IBM

Inventor： VERPLANKEN FABRICE JEAN ,  TROMBLEY MICHAEL RAYMOND ,  SIEGEL MICHAEL STEVEN ,  HEDDES MARCO C ,  CALVIGNAC JEAN LOUIS ,  BASS BRIAN MITCHELL

IPC: G06F12/00 ,  G06F5/06 ,  G06F5/14 ,  G06F12/02 ,  G06F12/08 ,  G06F13/00 ,  G06F13/14 ,  G06F13/16 ,  G06F13/38

Abstract: A bandwidth conserving queue manager for a FIFO buffer is provided, preferab ly on an ASIC chip and preferably including separate DRAM storage that maintains a FI FO queue which can extend beyond the data storage space of the FIFO buffer to provide additiona l data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multipl e queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffe r storage space in the FIFO buffers is exceeded, data are written to and read from the addition al data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a wa y that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.

公开(公告)号：CA2484508C

公开(公告)日：2009-12-22

申请号：CA2484508

申请日：2003-05-16

Applicant: IBM

Inventor： SIEGEL MICHAEL STEVEN ,  SABHIKHI RAVINDER KUMAR ,  RINALDI MARK ANTHONY ,  PEYRAVIAN MOHAMMAD

IPC: H04L47/724 ,  H04L12/40

Abstract: A Resource Reservation System includes a Token Generation Unit (TGU) which generates and circulates among nodes of a communications system a Slotted Token (SLT) message having sub-fields to carry identification number for eac h input port in a node and the resource available for each input port. On receiving the message the Resource Control Unit (RCU) in each node can write port identification number, available resource in appropriate sub-fields of the SLT message, and reserve resources in other nodes by adjusting informati on in the sub-field associated with the other nodes.

公开(公告)号：DE60042493D1

公开(公告)日：2009-08-13

申请号：DE60042493

申请日：2000-11-21

Applicant: IBM

Inventor： AYDEMIR METIN ,  BASS BRIAN MITCHELL ,  JEFFRIES CLARK DEBS ,  ROVNER SONIA KIANG ,  SIEGEL MICHAEL STEVEN ,  GALLO ANTHONY MATTEO ,  GORTI BRAHMANAND KUMAR ,  HEDDES MARCO

IPC: H04L47/30

Abstract: Methods, apparatus and program products for controlling a flow of a plurality of packets in a computer network are disclosed. The computer network includes a device defining a queue. The methods, apparatus and program products include determining a queue level for the queue and determining an offered rate of the plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, based on the queue level, the offered rate and a previous value of the transmission fraction so that the transmission fraction and the queue level are critically damped if the queue level is between at least a first queue level and a second queue level. Several embodiments are disclosed in which various techniques are used to determine the manner of the control.

公开(公告)号：AU2003230036B2

公开(公告)日：2007-09-13

申请号：AU2003230036

申请日：2003-05-16

Applicant: IBM

Inventor： SIEGEL MICHAEL STEVEN ,  PEYRAVIAN MOHAMMAD ,  SABHIKHI RAVINDER KUMAR ,  RINALDI MARK ANTHONY

IPC: H04L47/724 ,  H04L12/40

Abstract: A Resource Reservation System includes a Token Generation Unit (TGU) which generates and circulates among nodes of a communications system a Slotted Token (SLT) message having sub-fields to carry identification number for each input port in a node and the resource available for each input port. On receiving the message the Resource Control Unit (RCU) in each node can write port identification number, available resource in appropriate sub-fields of the SLT message, and reserve resources in other nodes by adjusting information in the sub-field associated with the other nodes.