公开(公告)号：SG137760A1

公开(公告)日：2007-12-28

申请号：SG2007033046

申请日：2007-05-10

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： CHONG YUNG FU ,  DEZFULIAN KEVIN K ,  LUO ZHIJIONG ,  ZHU HUILONG

Abstract: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of forming a strained channel transistor structure (200) on a substrate (202), comprising the steps of: forming a source stressor recess (225) comprising a deep source recess (219) and a source extension recess (221); forming a drain stressor recess (226) comprising a deep drain recess (220) and a drain extension recess (222); and subsequently forming a source stressor (227) in said source stressor recess (225) and a drain stressor (228) in said drain stressor recess (226). The deep source/drain and source/drain extension stressors are formed by an uninterrupted etch process and an uninterrupted epitaxy process.

公开(公告)号：DE602005024611D1

公开(公告)日：2010-12-16

申请号：DE602005024611

申请日：2005-12-13

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

公开(公告)号：SG152247A1

公开(公告)日：2009-05-29

申请号：SG2009025891

申请日：2006-11-28

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： LUO ZHIJIONG ,  CHONG YUNG FU ,  ZHU HUILONG

Abstract: There is provided a method of manufacturing a field effect transistor (FET) (100) that includes the steps of forming a gate structure (175) on a semiconductor substrate (105), and forming a recess (160) in the substrate and embedding a second semiconductor material (165) in the recess. The gate structure includes a gate dielectric layer (115), conductive layers (120, 130) and an insulating layer (125). Forming said gate structure includes a step of recessing the conductive layer (130) in the gate structure, and the steps of recessing the conductive layer and forming the recess (160) in the substrate are performed in a single step. There is also provided a FET device.

公开(公告)号：SG138528A1

公开(公告)日：2008-01-28

申请号：SG2007036023

申请日：2007-05-28

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： LUO ZHIJIONG ,  LUN ZHAO ,  HOLT JUDSON ROBERT ,  CHONG YUNG FU ,  ZHU HUILONG

Abstract: The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces (14A, 16A) with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate (10). Each surface recess preferably has a bottom surface (14, 16) that is parallel to the substrate surface (10A), which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces (14A, 16A) that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces (14A, 16A) of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces (14A, 16A) can be readily formed by crystallographic etching of the semiconductor substrate (10), followed by epitaxial growth of a semiconductor material.