公开(公告)号：DE10121309A1

公开(公告)日：2002-11-14

申请号：DE10121309

申请日：2001-05-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POECHMUELLER PETER ,  ERNST WOLFGANG ,  KRAUSE GUNNAR ,  KUHN JUSTUS ,  LUEPKE JENS ,  MUELLER JOCHEN ,  SCHITTENHELM MICHAEL

IPC: G01R31/319 ,  G11C29/48 ,  G11C29/00 ,  G01R31/3193

Abstract: Test circuit for a DUT comprises: (a) a test data generator (15) that generates reference test data as commanded by a control signal (b) a data output driver (25) for output of the generated reference test data and its delivery via a differential data bus to the DUT (c) a data input circuit for receipt of data from the DUT (d) a comparator circuit for comparison of the data from the DUT with the reference data to determine if it is operating correctly (e) whereby the data conducting pair (31, 36) of the differential data bus are configured to minimize signal transfer time differences. The differential data bus has one line carrying the data signal and the other the inverted signal with bus designed to minimize signal transfer time differences along the two lines.

公开(公告)号：DE10115879C1

公开(公告)日：2002-10-10

申请号：DE10115879

申请日：2001-03-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POECHMUELLER PETER ,  ERNST WOLFGANG ,  KRAUSE GUNNAR ,  KUHN JUSTUS ,  LUEPKE JENS ,  MUELLER JOCHEN ,  SCHITTENHELM MICHAEL

IPC: G01R31/3183 ,  G11C29/14 ,  G11C29/36 ,  G11C29/00

Abstract: A frequency multiplier multiplies low frequency input clock signal from a test unit by a predetermined multiplication factor to output a high frequency clock signal. The test unit generates a multi-row register selection control data vector having number of control data equivalent to the frequency multiplication factor. A multiplexer switches through data words stored in data registers based on a register selection control datum. An Independent claim is included for test data pattern generation method.

公开(公告)号：DE10111439A1

公开(公告)日：2002-09-26

申请号：DE10111439

申请日：2001-03-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POECHMUELLER PETER ,  ERNST WOLFGANG ,  KRAUSE GUNNAR ,  KUHN JUSTUS ,  LUEPKE JENS ,  MUELLER JOCHEN ,  SCHITTENHELM MICHAEL

IPC: G11C29/14 ,  G11C29/48 ,  G11C29/00

Abstract: The circuit has at least one controllable demultiplexer (22) with an input (21) for the signal to be delayed and several outputs (23); the input is connected to one of the outputs depending on a control signal. Several signal delay lines (27) with different lengths are connected to an output and the connected signal is delayed by a defined period proportional to the line length of the signal delay line.

公开(公告)号：DE10101999A1

公开(公告)日：2002-08-08

申请号：DE10101999

申请日：2001-01-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUEPKE JENS ,  ERNST WOLFGANG ,  KUHN JUSTUS ,  MUELLER JOCHEN ,  SCHITTENHELM MICHAEL ,  POECHMUELLER PETER ,  KRAUSE GUNNAR

IPC: G11C29/56 ,  G11C29/00

Abstract: The circuit has an address selection circuit (9) connected to first and second address memories (10,11) for storing first and second addresses, a multiplexer (15) connected to the address memories and to an address bus (3) and a command evaluation circuit (13) connected to the multiplexer and that controls it to apply the first or second address to the address bus depending on a command concerning the memory component. Independent claims are also included for the following: a method of generating data and testing a memory component.

公开(公告)号：DE10062404A1

公开(公告)日：2002-06-27

申请号：DE10062404

申请日：2000-12-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEITZ PETER ,  KUHN JUSTUS

IPC: G11C29/00

Abstract: The method reduces the number of memory cell addresses which are stored and processed during testing of a memory (3) by comparing a faulty memory cell address obtained by testing with a second fault address for a word and/or bit line to be repaired, with the faulty memory cell address only stored when it does not correspond to the second fault address. An Independent claim for a device for reducing the number of faulty memory cell addresses during testing of a memory is also included.

公开(公告)号：DE10060437A1

公开(公告)日：2002-06-13

申请号：DE10060437

申请日：2000-12-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEIDENHOEFER JUERGEN ,  POECHMUELLER PETER ,  KUHN JUSTUS ,  MUELLER JOCHEN ,  HUEBNER MICHAEL ,  KRAUSE GUNNAR

IPC: G01R1/02 ,  G01R31/28 ,  G01R31/319 ,  G11C29/00 ,  G11C29/48 ,  G01R31/26 ,  G01R31/3181 ,  H01L21/66 ,  H01L23/24

Abstract: The needle card device has a circuit board (70) for connection to signal lines of a test system and contact elements (36) for providing electrical conections with contact surfaces of the tested IC's (52). A carrier board (60) is provided with active modules (30), associated respectively with the tested IC's and inserted in the signal paths between the test system and the tested IC, with a heat dissipation device for removal of waste heat from each active module.

公开(公告)号：DE10060436A1

公开(公告)日：2002-03-28

申请号：DE10060436

申请日：2000-12-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEIDENHOEFER JUERGEN ,  POECHMUELLER PETER ,  KUHN JUSTUS ,  MUELLER JOCHEN ,  HUEBNER MICHAEL ,  KRAUSE GUNNAR

IPC: G01R31/319 ,  G11C29/48 ,  G11C29/56 ,  G01R31/3181 ,  G01R31/3177 ,  G11C29/00 ,  H01L21/66

Abstract: The device has connections for low frequency or LF signal communications with test equipment, especially for acquiring LF test signals such as data, control, address and clock signals, an arrangement for producing high frequency or HF test signals based on incoming LF test signals and second connections for HF signal communications with a circuit under test, especially for outputting HF test signals and receiving response signals from the circuit. The device has first connections (32a,32b) for low frequency signal communications with a test equipment (40), especially for acquiring low frequency test signals such as data, control, address and clock signals, an arrangement (38) for producing high frequency test signals based on incoming low frequency test signals and second connections (34a-34d) for high frequency signal communications with a circuit under test (52), especially for outputting high frequency test signals and receiving response signals from the circuit.