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    INTEGRATED MAGNETORESISTIVE SEMICONDUCTOR MEMORY ARRANGEMENT
    3.
    发明申请
    INTEGRATED MAGNETORESISTIVE SEMICONDUCTOR MEMORY ARRANGEMENT 审中-公开
    综合磁阻半导体存储器结构

    公开(公告)号：WO02084706A3

    公开(公告)日：2003-05-30

    申请号：PCT/DE0201256

    申请日：2002-04-05

    Applicant: INFINEON TECHNOLOGIES AG ,  WEITZ PETER

    Inventor： WEITZ PETER

    IPC: G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

    CPC classification number: G11C11/15 ,  H01L27/222

    Abstract: The invention relates to an integrated magnetoresistive semiconductor memory arrangement (MRAM), in which the MRAM memory cells (10) each lie at crossing points for the select lines (5, 6) embedded in various separate line planes (1, 2), into which a read/write current may be imprinted for describing each MRAM memory cell (10) and for reading information written therein. Said magnetoresistive semiconductor memory arrangement has selection lines (5, 6), for reading the information in a cell, which are in separate first and second line planes (1, 2), each in direct contact with the memory cells (10) and a third and fourth line plane (3, 4), physically and electrically separate from the first and second line plane, which have write selection lines (7, 8) for writing cell information.

    Abstract translation: 本发明涉及一种集成的磁阻半导体存储装置（MRAM），其中，所述MRAM存储单元（10）的每一个的不同的相互分离的线的平面（1,2）嵌入选择线的交叉点（5,6）是，在每一个用于描述每个MRAM -Speicherzelle（10）和用于读取写入其中的信息，读/写电流可以留下深刻的印象。 此磁阻半导体存储器装置是选择线（5,6）服务，用于读取放置分开的第一和第二导体平面的小区的信息，每一个都与存储单元的直接接触（10）（1，2）和第三和第四，第一和第二管理水平的 空间上分离并且电管理水平（3,4）连接到分配用于写入的小区信息的写入选择线（7,8）。

    4.
    发明专利
    未知

    公开(公告)号：DE102004049356B4

    公开(公告)日：2006-06-29

    申请号：DE102004049356

    申请日：2004-10-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： THOMAS JOCHEN ,  LUDEWIG SYLKE ,  GRAFE JUERGEN ,  WEITZ PETER

    IPC: H01L25/065

    Abstract: A semiconductor module having an internal semiconductor chip stack on a wiring substrate is disclosed. In one embodiment, the semiconductor chip stack has semiconductor chips which are arranged such that they are offset, the semiconductor chips having bonding connection pads in at least one edge region of their active top side. These bonding connection pads are electrically connected to the wiring substrate via bonding connections. In this case, the semiconductor chips are stacked on top of one another in an offset manner such that the bonding connection pads remain free of a semiconductor chip which is stacked on top of them. In this case, the semiconductor chips may be identical silicon chips which may differ, for example in pairs, in terms of their wiring structure for the centrally arranged contact areas in different edge regions.

    5.
    发明专利
    未知

    公开(公告)号：DE10139724A1

    公开(公告)日：2003-03-13

    申请号：DE10139724

    申请日：2001-08-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WEITZ PETER

    IPC: G11C7/10 ,  G11C29/26 ,  G11C29/00

    Abstract: An integrated memory including memory cells in a plurality of memory cell blocks, each memory cell block being assigned at least one dedicated data line and a register circuit that can be written outside the memory. At the start of a test operation, data is stored in the register circuits as reference data. During an access cycle, in each case in each of the memory cell blocks, a respective memory cell or a group of memory cells is selected, a respective read amplifier is activated and, in each of the register circuits, a comparison between the data read out and the reference data is carried out. As a result, the time required for the test operation of the memory is made comparatively low.

    8.
    发明专利
    未知

    公开(公告)号：DE102005010156A1

    公开(公告)日：2005-10-06

    申请号：DE102005010156

    申请日：2005-03-02

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GRAFE JUERGEN ,  HEDLER HARRY ,  POHL JENS ,  THOMAS JOCHEN ,  WEITZ PETER

    IPC: G11C5/14 ,  H01L23/48 ,  H01L23/50 ,  H01L25/065

    Abstract: An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die.

    10.
    发明专利
    未知

    公开(公告)号：DE10139724B4

    公开(公告)日：2004-04-08

    申请号：DE10139724

    申请日：2001-08-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WEITZ PETER

    IPC: G11C7/10 ,  G11C29/26 ,  G11C29/00

    Abstract: An integrated memory including memory cells in a plurality of memory cell blocks, each memory cell block being assigned at least one dedicated data line and a register circuit that can be written outside the memory. At the start of a test operation, data is stored in the register circuits as reference data. During an access cycle, in each case in each of the memory cell blocks, a respective memory cell or a group of memory cells is selected, a respective read amplifier is activated and, in each of the register circuits, a comparison between the data read out and the reference data is carried out. As a result, the time required for the test operation of the memory is made comparatively low.

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