公开(公告)号：DE602004021187D1

公开(公告)日：2009-07-02

申请号：DE602004021187

申请日：2004-06-03

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

IPC: G11C29/00 ,  G06F11/10 ,  G11C7/24 ,  G11C11/15 ,  G11C11/406

Abstract: The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.

公开(公告)号：DE60028099D1

公开(公告)日：2006-06-29

申请号：DE60028099

申请日：2000-01-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: G11C7/10 ,  G11C11/41 ,  G11C11/409 ,  G11C11/4096 ,  G11C11/417 ,  H03K19/017

Abstract: A high frequency driver circuit is described. The driver produces increased current flow at its output to decrease charging time, thereby enabling higher frequency operations. Increased current flow is achieved by providing an active control signal that increases the magnitude of the overdrive voltage applied to a driver transistor.

公开(公告)号：DE69834540D1

公开(公告)日：2006-06-22

申请号：DE69834540

申请日：1998-12-18

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C7/00 ,  G11C11/401 ,  G11C7/18 ,  G11C8/00 ,  G11C8/14 ,  G11C11/408 ,  G11C11/409 ,  G11C16/06

Abstract: Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F , includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.

公开(公告)号：DE69829618T2

公开(公告)日：2006-04-27

申请号：DE69829618

申请日：1998-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  HOENIGSCHMID HEINZ

IPC: G11C8/00 ,  G11C11/41 ,  G11C8/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/108

Abstract: Disclosed is a multiple bank semiconductor memory (40) (e.g., DRAM) capable of overlapping write/read operation to/from memory cells of different banks (MAa, MAb), and having a space efficient layout. Chip size is kept small by employing a single column decoder (44) for different banks, and a hierarchical column select line architecture, with bit line switches (59, 61, 63, 65) of different columns having a shared active area such as a common source region. In an illustrative embodiment, global column select lines (GCSL1-GCSL(N/K)) selectively activate global bit line switches (67, 68) which are coupled to bank-specific data lines (LDQ, LDQ). Several bank bit line switches (59-66) are coupled to each global bit line switch, with two or more bank bit line switches of different columns having a shared diffusion region to realize a compact layout.

公开(公告)号：DE69833415D1

公开(公告)日：2006-04-20

申请号：DE69833415

申请日：1998-09-21

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI

IPC: G11C7/06 ,  G11C11/403 ,  G11C5/02 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108

Abstract: A semiconductor memory having a plurality of memory cells arranged in rows and columns includes a bank of sense amplifiers disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier in the bank disposed in a sense amplifier region between a pair of complementary bit lines of an associated column. A master data line (MDQ) switch is located in a sense amplifier region occupying a corresponding row-wise space to at least one driver to provide space efficient placement thereof.

公开(公告)号：DE60016987T2

公开(公告)日：2006-03-30

申请号：DE60016987

申请日：2000-01-27

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HANSON DAVID RUSSELL ,  MUELLER GERHARD

IPC: G11C11/413 ,  H03K19/00 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/417 ,  H03K5/00 ,  H04L7/00 ,  H04L7/02 ,  H04L25/40

Abstract: A synchronized data capture circuit configured to synchronize capturing of data in a data signal with a timing signal in an integrated circuit. The synchronized data circuit employs voltage signals having a reduced voltage level, the data signal and the timing signal having a first voltage level higher than the reduced voltage level. The synchronized data capture circuit includes a timing driver circuit arranged to receive the timing signal. The timing driver circuit outputs a reduced voltage timing signal having the reduced voltage level. There is included a data driver circuit arranged to receive the data signal and the timing signal, the data driver outputting a reduced voltage clocked data signal having the reduced voltage level. There is further included a data clocking circuit coupled to the timing driver circuit and the data driver circuit. The data clocking circuit is arranged to receive the reduced voltage timing signal and the reduced voltage clocked data signal. The data clocking circuit outputs a synchronized capture data signal having the first voltage level higher than the reduced voltage level.

公开(公告)号：DE60017621T2

公开(公告)日：2006-03-23

申请号：DE60017621

申请日：2000-02-18

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: G11C11/409 ,  H03K19/017 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/41 ,  G11C11/417 ,  H03K17/06 ,  H03K19/0175

公开(公告)号：DE69829618D1

公开(公告)日：2005-05-12

申请号：DE69829618

申请日：1998-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  HOENIGSCHMID HEINZ

IPC: G11C11/41 ,  G11C8/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C8/00 ,  H01L27/02

Abstract: Disclosed is a multiple bank semiconductor memory (40) (e.g., DRAM) capable of overlapping write/read operation to/from memory cells of different banks (MAa, MAb), and having a space efficient layout. Chip size is kept small by employing a single column decoder (44) for different banks, and a hierarchical column select line architecture, with bit line switches (59, 61, 63, 65) of different columns having a shared active area such as a common source region. In an illustrative embodiment, global column select lines (GCSL1-GCSL(N/K)) selectively activate global bit line switches (67, 68) which are coupled to bank-specific data lines (LDQ, LDQ). Several bank bit line switches (59-66) are coupled to each global bit line switch, with two or more bank bit line switches of different columns having a shared diffusion region to realize a compact layout.

公开(公告)号：DE69923097D1

公开(公告)日：2005-02-17

申请号：DE69923097

申请日：1999-03-09

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: H03K19/0175 ,  B24B9/06 ,  B24B37/04 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/094

Abstract: There is disclosed a tri-state buffer circuit for receiving an input signal at a buffer input node and transmitting, responsive to a buffer enable signal, an output signal at a buffer output node. The buffer circuit includes an input stage (202) coupled to the buffer input node (208). The input stage (202) is configured to receive, when the buffer enable signal is enabled, the input signal. The buffer circuit further includes a level shifter stage (204) coupled to the input stage (202). The level shifter stage (204) is arranged to output, when the buffer enable signal is enabled, a set of level shifter stage control signals responsive to the input signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the input signal. The buffer circuit also includes an output stage (206) coupled to the level shifter stage (204). The output stage (206) is configured to output, when the buffer enable signal is enabled, the output signal (210) on the buffer output node responsive to the set of level shifter stage control signals. The voltage range of the output signal is lower than the voltage range of the set of level shifter stage control signals. The output stage (206) decouples the buffer output node from the input stage and the level shifter stage when the buffer enable signal is disabled.

公开(公告)号：DE10245179A1

公开(公告)日：2003-05-15

申请号：DE10245179

申请日：2002-09-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  PARK YOUNG-JIN

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: An integrated circuit comprises first lines (220) on a first plane (260); and second lines (225) on a second plane (265). At least one of the first or second lines comprises a non-rectangular cross-section. An Independent claim is also included for the production of an integrated circuit. Preferred Features: At least one of the first or second lines comprises a non-vertical side wall which tapers toward the other side wall. At least one of the first or second lines has a triangular cross-section. The second lines of the second plane are arranged over the first lines of the first plane.