公开(公告)号：AT407415T

公开(公告)日：2008-09-15

申请号：AT99947346

申请日：1999-09-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GAIL MARKUS ,  POCKRANDT WOLFGANG ,  WEDEL ARMIN ,  HESS ERWIN

IPC: G06F12/14 ,  G07F7/10 ,  G06F21/02 ,  G06F21/24 ,  G06K19/073 ,  G11C16/10 ,  H03K19/173

Abstract: A circuit configuration includes at least one nonvolatile, electrically erasable and writable memory area. Each memory area is assigned a nonvolatile, electrically writable and erasable flag memory, which is connected through an address line, a programming line and an authentication line to the assigned memory area, a programming voltage source and a data verification circuit. In the event of an alteration in the content of a memory area, the state of the associated flag memory is changed and, after verification of the programmed memory area content, the flag memory is returned to its basic state.

公开(公告)号：AT257294T

公开(公告)日：2004-01-15

申请号：AT99936340

申请日：1999-05-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ALLINGER ROBERT ,  HOLLFELDER ROBERT ,  POCKRANDT WOLFGANG ,  WEDEL ARMIN

IPC: G07F7/10 ,  H03K21/40

Abstract: A method of operating a multistage counter in only one counting direction includes the step of changing a counter reading of a single-stage auxiliary counter at given counter readings of the multistage counter. The single-stage auxiliary counter and the multistage counter can only be changed in one counting direction. Respective counter readings of the multistage counter and of the single-stage auxiliary counter are registered. Values of the respective counter readings of the single-stage auxiliary counter and of the multistage counter are compared with one another, and an indicator signal is generated based on a comparison result determined in the comparing step.

公开(公告)号：DE10161046A1

公开(公告)日：2003-07-03

申请号：DE10161046

申请日：2001-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POCKRANDT WOLFGANG

IPC: G06K19/073 ,  G06F11/07

Abstract: The invention relates to a circuit configuration in which two parallel subcircuits (1, 2) having the same functionality receive an identical input signal (input). The output signals (output) of the two parallel subcircuits are compared in a joint comparative configuration. The two subcircuits are designed differently in terms of their sensitivity to changes in the environment parameters or operation parameters. Differences in the output signal are an indication of inadmissible environment parameters. A signal generating an alarm (alarm) is issued when the output signals differ.

公开(公告)号：MXPA02005267A

公开(公告)日：2003-02-12

申请号：MXPA02005267

申请日：2002-05-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POCKRANDT WOLFGANG

IPC: G07F7/08 ,  G07F7/10 ,  G06M3/12 ,  H03K21/40

Abstract: Se presenta un procedimiento para hacer funcionar un contador de varias etapas en unicamente una direccion de conteo realizandose los siguientes pasos: - variar el valor numerico de un contador auxiliar de una etapa que solo puede ser variado en una direccion de conteo, por lo cual son predeterminados los estados de valor numerico del contador de varias etapas; - captar los estados de valor numerico correspondientes del contador de varias etapas y del contador auxiliar de una etapa; y - generar los primeros datos de autenticacion relacionando el valor numerico del contador auxiliar con los datos adicionales.

公开(公告)号：DE59804903D1

公开(公告)日：2002-08-29

申请号：DE59804903

申请日：1998-04-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POCKRANDT WOLFGANG

IPC: G06F1/00 ,  G06F12/14 ,  G06F15/16 ,  G06F21/44 ,  H04L29/06

Abstract: The system checks whether authorization exists for at least two data processing devices to exchange data with one another. In the preferred embodiment, both data processing devices are of identical design. Check data are simultaneously produced, in response to a trigger signal, in both data processing devices. The check data are compared with one another in the data processing device to which a control function has been allocated.

公开(公告)号：AT219260T

公开(公告)日：2002-06-15

申请号：AT97932758

申请日：1997-07-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZELLNER ANGELA ,  RAESCHMEIER ANDREAS ,  POCKRANDT WOLFGANG

IPC: H01L21/822 ,  G06F1/00 ,  G06F12/14 ,  G06F21/87 ,  H01L23/525 ,  H01L23/544 ,  H01L23/58 ,  H01L27/04

Abstract: A semiconductor circuit, in particular for use in an integrated module, has at least one operational assembly with a drive circuit, such as a microprocessor, and a data memory. The semiconductor circuit has at least one initialization assembly for testing and/or for initializing the operational assembly. A disconnectable connecting line connects the operational assembly to the initialization assembly. In order to increase reliability, the initialization assembly is permanently disconnected from the operational assembly, by disconnecting the connecting lines, after the semiconductor circuit has been completed. In order to make it more difficult to reactivate the disconnected connecting lines, the semiconductor circuit has a potential line connected to the initialization assembly and/or to the operational assembly in a region of the connecting line. The initialization assembly and/or the operational assembly are configured in such a way that, when the potential line is connected to the connecting line, the initialization assembly is placed in an inactive state.

公开(公告)号：DE59803351D1

公开(公告)日：2002-04-18

申请号：DE59803351

申请日：1998-07-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POCKRANDT WOLFGANG ,  SEDLAK HOLGER ,  VIEHMANN HANS-HEINRICH

IPC: G11C16/04 ,  G11C16/06

Abstract: The invention relates to a semiconductor memory having a non-volatile two-transistor memory cell which has an N-channel selection transistor and an N-channel memory transistor. The drive circuitry for the cell includes a P-channel transfer transistor. A transfer channel is connected to a row line leading to the memory cell. This enables the voltages required for programming to be obtained with relatively little technological complexity.

公开(公告)号：DE19903349C2

公开(公告)日：2001-12-13

申请号：DE19903349

申请日：1999-01-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LAUTERBACH CHRISTL ,  WEBER WERNER ,  POCKRANDT WOLFGANG

IPC: H01L23/525 ,  H01L27/108 ,  H01L27/12 ,  H01L27/112 ,  H01L21/768 ,  H01L21/8246

公开(公告)号：AT206242T

公开(公告)日：2001-10-15

申请号：AT98966779

申请日：1998-12-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POCKRANDT WOLFGANG

IPC: G07F7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10

Abstract: A method for reliably changing the value of a data medium having at least two volatile memory areas for storing a currently valid value. Each memory area has at least one associated nonvolatile control memory cell whose state defines the currently valid memory area. The current value is first written to an invalid memory area. A previously valid memory area and the associated control memory cell are then erased simultaneously and the control memory cell for the memory area to which information had previously been written is programmed, likewise simultaneously, so that the latter memory area can be recognized as the valid memory area.

公开(公告)号：DE50214473D1

公开(公告)日：2010-07-15

申请号：DE50214473

申请日：2002-06-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GAIL MARKUS ,  HESS ERWIN ,  POCKRANDT WOLFGANG ,  WEDEL ARMIN

IPC: H04L9/32 ,  G07F7/08 ,  G07F7/10 ,  H03K3/84