公开(公告)号：GB2433624A

公开(公告)日：2007-06-27

申请号：GB0706172

申请日：2007-03-29

Applicant: INTEL CORP

Inventor： VOGT PETE

IPC: G06F11/10 ,  G06F12/08 ,  G06F13/28 ,  G11C7/10 ,  G11C29/52

Abstract: Methods and apparatus for use with memory systems and memory modules are included among the embodiments. In exemplary systems, error-correction coding (ECC) data is temporally multiplexed with user data on the same data bus lines in a burst mode transfer, such that separate chips and data lines are not required to support ECC. The memory devices on the modules each contain additional indirectly addressable ECC segments associated with addressable segments of the device. The temporally multiplexed ECC data is read from and written to the indirectly addressable segment associated with the addressable data transmitted in the burst mode transfer. In some embodiments, two types of burst modes are supported, one which includes ECC data and one which does not.This allows one type of memory module to support both ECC and non-ECC systems, and in some cases to use ECC for some data and not for other data in the same system. Other embodiments are described and claimed.

公开(公告)号：HK1086375A1

公开(公告)日：2006-09-15

申请号：HK06108457

申请日：2006-07-29

Applicant: INTEL CORP

Inventor： HALBERT JOHN ,  FREEMAN CHRIS ,  WILLIAMS MICHAEL ,  BAINS KILJIT ,  ELLIS ROBERT ,  VOGT PETE

IPC: G06F13/16 ,  G09F20090101

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.

公开(公告)号：DE112011105909T5

公开(公告)日：2014-09-11

申请号：DE112011105909

申请日：2011-12-02

Applicant: INTEL CORP

Inventor： SHOEMAKER KENNETH ,  VOGT PETE ,  SCHAEFER ANDRE ,  MORROW WARREN ,  KIM JIN ,  HALBERT JOHN

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

Abstract: Dynamische Operationen für Operationen für einen Stapelspeicher mit Schnittstelle, die Offset-Kopplungsstrukturen bereitstellt. Eine Ausführungsform des Speichergeräts schließt ein Systemelement und einen Speicherstapel ein, der mit dem Systemelement gekoppelt ist, wobei der Speicherstapel eine oder mehrere Speicherchiplagenschichten einschließt. Jede Speicherchiplagenschicht schließt eine erste Fläche und eine zweite Fläche ein, wobei die zweite Fläche jeder Speicherchiplagenschicht eine Schnittstelle einschließt, um Datenschnittstellenpins der Speicherchiplagenschicht mit Datenschnittstellenpins einer ersten Fläche eines gekoppelten Elementes zu koppeln. Die Schnittstelle jeder Speicherchiplagenschicht schließt Verbindungen ein, die einen Offset zwischen jedem der Datenschnittstellenpins der Speicherchiplagenschicht und einem entsprechenden Datenschnittstellenpin der Datenschnittstellenpins des gekoppelten Elementes bereitstellen.

公开(公告)号：AT524810T

公开(公告)日：2011-09-15

申请号：AT06773852

申请日：2006-06-22

Applicant: INTEL CORP

Inventor： VOGT PETE

IPC: G11C7/20

Abstract: A memory device may determine its device ID in response to the order of a received training pattern. The training pattern may be transmitted over swizzled signal lines to multiple memory devices arranged in a logical stack. Each memory device may be packaged on a substrate having the swizzled signal lines. The memory devices may be physically stacked or planar. Other embodiments are described and claimed.

公开(公告)号：GB2441082B8

公开(公告)日：2011-03-09

申请号：GB0722948

申请日：2006-06-22

Applicant: INTEL CORP

Inventor： VOGT PETE

IPC: G11C7/20 ,  G11C11/4072

Abstract: A memory device may determine its device ID in response to the order of a received training pattern. The training pattern may be transmitted over swizzled signal lines to multiple memory devices arranged in a logical stack. Each memory device may be packaged on a substrate having the swizzled signal lines. The memory devices may be physically stacked or planar. Other embodiments are described and claimed.

公开(公告)号：GB2441082A8

公开(公告)日：2011-03-09

申请号：GB0722948

申请日：2006-06-22

Applicant: INTEL CORP

Inventor： VOGT PETE

Abstract: A memory device may determine its device ID in response to the order of a received training pattern. The training pattern may be transmitted over swizzled signal lines to multiple memory devices arranged in a logical stack. Each memory device may be packaged on a substrate having the swizzled signal lines. The memory devices may be physically stacked or planar. Other embodiments are described and claimed.

公开(公告)号：DE602004020495D1

公开(公告)日：2009-05-20

申请号：DE602004020495

申请日：2004-11-05

Applicant: INTEL CORP

Inventor： HALBERT JOHN ,  FREEMAN CHRIS ,  WILLIAMS MICHAEL ,  BAINS KILJIT ,  ELLIS ROBERT ,  VOGT PETE

IPC: G09F13/16 ,  G06F13/16

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.

公开(公告)号：GB2433624B

公开(公告)日：2008-10-15

申请号：GB0706172

申请日：2007-03-29

Applicant: INTEL CORP

Inventor： VOGT PETE

IPC: G06F11/10 ,  G06F12/08 ,  G06F13/28 ,  G11C7/10 ,  G11C29/52

Abstract: Methods and apparatus for use with memory systems and memory modules are included among the embodiments. In exemplary systems, error-correction coding (ECC) data is temporally multiplexed with user data on the same data bus lines in a burst mode transfer, such that separate chips and data lines are not required to support ECC. The memory devices on the modules each contain additional indirectly addressable ECC segments associated with addressable segments of the device. The temporally multiplexed ECC data is read from and written to the indirectly addressable segment associated with the addressable data transmitted in the burst mode transfer. In some embodiments, two types of burst modes are supported, one which includes ECC data and one which does not. This allows one type of memory module to support both ECC and non-ECC systems, and in some cases to use ECC for some data and not for other data in the same system. Other embodiments are described and claimed.

公开(公告)号：DE112005003273T5

公开(公告)日：2008-04-17

申请号：DE112005003273

申请日：2005-12-29

Applicant: INTEL CORP

Inventor： VOGT PETE

IPC: H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L25/065

Abstract: An embedded heat spreader includes a semiconductor die, an elastomer layer attached to the die, a tape lead attached to the elastomer, a portion of the tape lead exposed through the elastomer to connect with the die, a polymer resin attached to the tape lead, and a thermally conductive substrate attached to the polymer resin such that the thermally conductive substrate can spread heat from the semiconductor die.

公开(公告)号：GB2438528A

公开(公告)日：2007-11-28

申请号：GB0712810

申请日：2005-12-29

Applicant: INTEL CORP

Inventor： VOGT PETE

IPC: H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L25/065

Abstract: In some embodiments an apparatus may comprise a semiconductor die, an elastomer layer attached to the die, a tape lead attached to the elastomer, a portion of the tape lead exposed through the elastomer to connect with the die, a polymer resin attached to the tape lead, and a thermally conductive substrate attached to the polymer resin such that the thermally conductive substrate can spread heat from the semiconductor die.