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    Die Interconnect Substrates, a Semiconductor Device and a Method for Forming a Die Interconnect Substrate
    33.
    发明申请
    Die Interconnect Substrates, a Semiconductor Device and a Method for Forming a Die Interconnect Substrate 审中-公开

    公开(公告)号：US20180286812A1

    公开(公告)日：2018-10-04

    申请号：US15475175

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Rahul Jain ,  Ji Yong Park ,  Kyu Oh Lee

    IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

    ELECTRONIC DEVICE PACKAGE INCLUDING A CAPACITOR
    37.
    发明申请
    ELECTRONIC DEVICE PACKAGE INCLUDING A CAPACITOR 有权

    公开(公告)号：US20210151393A1

    公开(公告)日：2021-05-20

    申请号：US17158634

    申请日：2021-01-26

    Applicant: Intel Corporation

    Inventor： Brandon C Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D Ecton

    IPC: H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48

    Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

    SUBSTRATE EMBEDDED HEAT PIPE
    40.
    发明申请
    SUBSTRATE EMBEDDED HEAT PIPE 审中-公开

    公开(公告)号：US20200176355A1

    公开(公告)日：2020-06-04

    申请号：US16209861

    申请日：2018-12-04

    Applicant: Intel Corporation

    Inventor： Robert A. May ,  Kristof Darmawikarta ,  Rahul Jain ,  Lilia May ,  Maroun Moussallem ,  Prithwish Chatterjee

    IPC: H01L23/473 ,  H01L23/373 ,  H05K7/20

    Abstract: A semiconductor device package structure is provided, which includes a substrate, one or more dies coupled to the substrate, and a heat pipe device. In an example, the heat pipe device may include a conduit that is at least partially embedded within the substrate. The heat pipe device may have a first region coupled to the one or more dies. In an example, the conduit may include a first path for flow of vapor from the first region to an opposing second region. The conduit may further include a second path for flow of liquid from the second region to the first region.

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