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    COOLER FOR SEMICONDUCTOR DEVICES
    31.
    发明申请
    COOLER FOR SEMICONDUCTOR DEVICES 审中-公开
    冷却器用于半导体器件

    公开(公告)号：US20170062306A1

    公开(公告)日：2017-03-02

    申请号：US14839510

    申请日：2015-08-28

    Applicant: Intel IP Corporation

    Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Christian Geissler ,  Alexandra Atzesdorfer ,  Sonja Koller

    IPC: H01L23/427 ,  H01L23/373

    CPC classification number: H01L23/3737 ,  G06F1/203 ,  G06F2200/201 ,  H01L23/373 ,  H01L23/427 ,  H01L2224/16225 ,  H01L2924/15311

    Abstract: Embodiments of the present disclosure relate to a cooler for semiconductor devices. The semiconductor device may be electrically coupleable to a power source. The device may generate heat when the power source supplies power to the device during use of the device. The cooler may be coupled to one or more surfaces of the device. The cooler may include a hydrophilic material to adsorb water from ambient air. During operation of the device, the cooler may cool the device by conduction of heat away from the device to the cooler. The cooler may include water that is evaporated during use of the device to increase cooling capacity of the cooler. The cooler may be recharged with water from humidity in air when the device is not operated or operated at a lower power level. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例涉及一种用于半导体器件的冷却器。 半导体器件可以电耦合到电源。 当设备使用期间电源向设备供电时，设备可能会产生热量。 冷却器可以联接到装置的一个或多个表面。 冷却器可以包括用于从环境空气中吸附水的亲水材料。 在设备运行期间，冷却器可以通过将热量从设备传导到冷却器来冷却设备。 冷却器可以包括在使用装置期间蒸发的水以增加冷却器的冷却能力。 当设备未在较低功率水平下操作或操作时，冷却器可能会在空气中从潮湿的水中充电。 可以描述和/或要求保护其他实施例。

    Semiconductor die package with more than one hanging die
    32.
    发明授权
    Semiconductor die package with more than one hanging die 有权

    公开(公告)号：US10854590B2

    公开(公告)日：2020-12-01

    申请号：US15776378

    申请日：2015-12-23

    Applicant: Intel IP Corporation

    Inventor： Sven Albers ,  Klaus Reingruber ,  Richard Patten ,  Georg Seidemann ,  Christian Geissler

    IPC: H01L23/02 ,  H01L25/00 ,  H01L25/065 ,  H05K1/11

    Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.

    Integrated circuit package assemblies including a chip recess
    33.
    发明授权
    Integrated circuit package assemblies including a chip recess 有权

    公开(公告)号：US10714455B2

    公开(公告)日：2020-07-14

    申请号：US16215449

    申请日：2018-12-10

    Applicant: Intel IP Corporation

    Inventor： Georg Seidemann ,  Klaus Reingruber

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L25/00 ,  H01L23/367 ,  H01L23/538

    Abstract: IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be reduced relative to its thickness during the molding process. Another IC chip, heat spreader, etc. may then occupy the resultant recess framed by the molding compound to achieve a fine stacking pitch. In some embodiments, a package-on-package (PoP) assembly includes a center-molded IC chip flip-chip-bonded to a first package substrate. A second substrate to which a second IC chip is flip-chip bonded is then electrically coupled to the first substrate by through-molding vias. Within the PoP assembly, the second IC chip may be disposed back-to-back with the center-molded IC chip so as to occupy the recess framed by the molding compound.

    DEVICE CONTAINING AND METHOD OF PROVIDING CARBON COVERED COPPER LAYER
    34.
    发明申请
    DEVICE CONTAINING AND METHOD OF PROVIDING CARBON COVERED COPPER LAYER 审中-公开

    公开(公告)号：US20200006263A1

    公开(公告)日：2020-01-02

    申请号：US16025575

    申请日：2018-07-02

    Applicant: Intel IP Corporation

    Inventor： Georg Seidemann

    IPC: H01L23/00 ,  H01L23/29 ,  H05K1/09

    Abstract: A device and method of preventing corrosion of a copper layer in a PCB is disclosed. A first dielectric is disposed on a substrate. A copper layer is plated in an opening in the first dielectric and, after conditioning the copper layer, a redistribution layer is plated on the copper layer. A solder resist layer is disposed above the copper layer. A solder ball is disposed in an opening in the solder resist layer. The solder ball is in conductive contact with the copper layer and in physical contact with the redistribution layer. A non-conductive carbon layer is disposed on and in contact with the redistribution layer or tsi-diehe solder resist layer. The carbon layer is substantially thinner than the copper layer and acts as a diffusion barrier to moisture for the copper layer.

    THERMAL CONTACTS AT PERIPHERY OF INTEGRATED CIRCUIT PACKAGES
    35.
    发明申请
    THERMAL CONTACTS AT PERIPHERY OF INTEGRATED CIRCUIT PACKAGES 审中-公开

    公开(公告)号：US20190393125A1

    公开(公告)日：2019-12-26

    申请号：US16015334

    申请日：2018-06-22

    Applicant: Intel IP Corporation

    Inventor： Sonja Koller ,  Vishnu Prasad ,  Georg Seidemann

    IPC: H01L23/367 ,  H01L23/31 ,  H01L21/56

    Abstract: Present disclosure relates to IC packages with integrated thermal contacts. In some embodiments, an IC package includes a package substrate, an IC die that is coupled to the package substrate, and at least one thermal contact for coupling to at least a portion of a heat exchanger, where the thermal contact is limited to being in a region located at a periphery of the IC package. In some embodiments, thermal contacts are such that at least a portion of a heat exchanger is to be attached on the side of the IC package. In some embodiments, thermal contacts may be provided within a recessed portion at the periphery of the IC package. Providing a thermal contact at a periphery of an IC package may enable improved cooling options, especially for systems where there is no or limited space for providing conventional heat exchangers on the top of the package.

    INTERPOSER WITH CONDUCTIVE ROUTING EXPOSED ON SIDEWALLS
    40.
    发明申请
    INTERPOSER WITH CONDUCTIVE ROUTING EXPOSED ON SIDEWALLS 审中-公开

    公开(公告)号：US20180342431A1

    公开(公告)日：2018-11-29

    申请号：US15778410

    申请日：2015-12-18

    Applicant: Intel IP Corporation

    Inventor： Klaus Reingruber ,  Christian Geissler ,  Georg Seidemann ,  Sonja Koller

    IPC: H01L23/13 ,  H01L23/498

    Abstract: An electronic assembly that includes an electronic component; and an interposer that includes a body having upper and lower surfaces and side walls extending between the upper and lower surfaces, the interposer further including conductive routings that are exposed on at least one of the side walls, wherein the electronic component is connected directly to the interposer. The conductive routings are exposed on each side wall and on the upper and lower surfaces. The electronic assembly may further includes a substrate having a cavity such that the interposer is within the cavity, wherein the cavity includes sidewalls and substrate includes conductive traces that are exposed from the sidewalls of the cavity, wherein the conductive traces that are exposed from the sidewalls of the cavity are electrically connected directly to the conductive routings that are exposed on at least one of the side walls of the interposer.

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