公开(公告)号：US10784033B2

公开(公告)日：2020-09-22

申请号：US16367200

申请日：2019-03-27

Applicant: Intel IP Corporation

Inventor： Andreas Wolter ,  Thorsten Meyer ,  Gerhard Knoblinger

IPC: H01L23/64 ,  H01F17/00 ,  H01F41/04 ,  H01L23/522 ,  H01L23/00 ,  H01F27/28

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

公开(公告)号：US20190221349A1

公开(公告)日：2019-07-18

申请号：US16367200

申请日：2019-03-27

Applicant: Intel IP Corporation

Inventor： Andreas Wolter ,  Thorsten Meyer ,  Gerhard Knoblinger

IPC: H01F17/00 ,  H01L23/64 ,  H01F41/04

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

公开(公告)号：US10150668B2

公开(公告)日：2018-12-11

申请号：US15484765

申请日：2017-04-11

Applicant: Intel IP Corporation

Inventor： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC: H01L27/14 ,  B81C1/00 ,  B81B7/00

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

公开(公告)号：US20170217766A1

公开(公告)日：2017-08-03

申请号：US15484765

申请日：2017-04-11

Applicant: Intel IP Corporation

Inventor： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00238 ,  B81B7/008 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/10 ,  B81B2207/012 ,  B81B2207/053 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/0023 ,  B81C2203/0792 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

公开(公告)号：US08779564B1

公开(公告)日：2014-07-15

申请号：US13803143

申请日：2013-03-14

Applicant: Intel IP Corporation

Inventor： Mikael Knudsen ,  Thorsten Meyer ,  Saravana Maruthamuthu ,  Andreas Wolter ,  Georg Seidemann ,  Pablo Herrero ,  Pauli Jaervinen

IPC: H01L23/552 ,  H01L27/06

CPC classification number: H01L23/552 ,  H01L23/295 ,  H01L23/48 ,  H01L23/66 ,  H01L24/19 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2223/6688 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01Q1/2283 ,  H01Q9/0414 ,  H01Q9/0421 ,  H01Q23/00 ,  H01L2924/00

Abstract: A semiconductor device may include: a chip; a chip packaging structure at least partially surrounding the chip and having a receiving region configured to receive a first capacitive coupling structure; a first capacitive coupling structure disposed in the receiving region; and a second capacitive coupling structure disposed over the first capacitive coupling structure and capacitively coupled to the first capacitive coupling structure.

Abstract translation: 半导体器件可以包括：芯片; 芯片封装结构至少部分地围绕芯片并且具有被配置为接收第一电容耦合结构的接收区域; 设置在所述接收区域中的第一电容耦合结构; 以及设置在所述第一电容耦合结构上并且电容耦合到所述第一电容耦合结构的第二电容耦合结构。

公开(公告)号：US10290412B2

公开(公告)日：2019-05-14

申请号：US15036786

申请日：2015-06-25

Applicant: Intel IP Corporation

Inventor： Andreas Wolter ,  Thorsten Meyer ,  Gerhard Knoblinger

IPC: H01L23/64 ,  H01F17/00 ,  H01F41/04 ,  H01F27/28

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

公开(公告)号：US10056352B2

公开(公告)日：2018-08-21

申请号：US14329717

申请日：2014-07-11

Applicant: Intel IP Corporation

Inventor： Thorsten Meyer

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/538 ,  H01L23/52 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/0655 ,  H01L21/568 ,  H01L24/24 ,  H01L24/25 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/8203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/15311

Abstract: An apparatus includes at least a first IC die and a second IC die. Bottom surfaces of the first and second IC dice include a first plurality of connection pads and top surfaces of the first and second IC dice include a second plurality of connection pads. The apparatus also includes a layer of non-conductive material covering the top surfaces of the first and second IC dice, a plurality of through-vias, first conductive interconnect between at least a portion of the first plurality of connection pads and at least one through via, and second conductive interconnect on a top surface of the layer of non-conductive material that provides electrical continuity between at least a portion of the second plurality of connection pads and at least one through-via of the plurality of through-vias.

公开(公告)号：US20180186627A1

公开(公告)日：2018-07-05

申请号：US15857461

申请日：2017-12-28

Applicant: Intel IP Corporation

Inventor： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00238 ,  B81B7/008 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/10 ,  B81B2207/012 ,  B81B2207/053 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/0023 ,  B81C2203/0792 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

公开(公告)号：US09663353B2

公开(公告)日：2017-05-30

申请号：US14403571

申请日：2013-06-28

Applicant: Intel IP Corporation

Inventor： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC: H01L27/14 ,  B81B7/00 ,  B81C1/00

CPC classification number: B81C1/00238 ,  B81B7/008 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/10 ,  B81B2207/012 ,  B81B2207/053 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/0023 ,  B81C2203/0792 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

公开(公告)号：US20170148698A1

公开(公告)日：2017-05-25

申请号：US15427984

申请日：2017-02-08

Applicant: Intel IP Corporation

Inventor： Thorsten Meyer ,  Andreas Wolter

IPC: H01L23/31 ,  H01L23/522 ,  H01L21/683 ,  H01L21/56 ,  H01L25/18 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/96 ,  H01L25/18 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0603 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/96 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11

Abstract: Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a semiconductor device package has a semiconductor substrate having circuitry formed on the substrate. A plurality of conductive connection pads are on the semiconductor substrate to connect to the circuitry. A post is on each of a subset of the connection pads, the posts being formed of a conductive material. A dielectric layer is over the semiconductor substrate including over the connection pads and the posts. Filled vias are over each connection pad that is not of the subset and over each post of the subset of the connection pads and a connector os over each filled via